• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.8A
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• pp.777-784
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• 2010

Recently, the necessity of underwater communication and demand for transmitting and receiving various data such as voice or high resolution image data are increasing as well. The performance of underwater acoustic communication system is influenced by characteristics of the underwater communication channels. Especially, ISI(inter symbol interference) occurs because of delay spread according to multi-path and communication performance is degraded. In this paper, we study the OFDM technique to overcome the delay spread in underwater channel and by using CP, we compensate for delay spread. But PAPR which OFDM system has problem is very high. Therefore, we use DFT-spread OFDM method to avoid nonlinear distortion by high PAPR and to improve efficiency of amplifier. DFT-spread OFDM technique obtains high PAPR reduction effect because of each parallel data loads to all subcarrier by DFT spread processing before IFFT. In this paper, we show performance about delay spread through OFDM system and verify method that DFT spread OFDM is more suitable than OFDM for underwater communication. And we analyze performance according to two subcarrier mapping methods(Interleaved, Localized). Through the simulation results, performance of DFT spread OFDM is better about 5~6dB at $10^{-4}$ than OFDM. When compared to BER according to subcarrier mapping, Interleaved method is better about 3.5dB at $10^{-4}$ than Localized method.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.12 s.103
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• pp.1229-1238
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• 2005

OFDM(Orthogonal Frequency Division Multiplexing) communications system is very attractive for the high data rate wireless transmission. However, it may be distorted in the nonlinear HPA(High Power Amplifier) since OFDM signal has hish PAPR(Peak-to-Average Power Ratio). In this paper, a new method using control tone is studied for reducing the PAPR and we call it PCT(PAPR Control Tone) method. This proposed PCT method is to assign control tones for PAPR reduction at the predefined sub-carriers. After IFFT(Inverse Fast Fourier Transform) and PAPR calculation, the OFDM data signal of the lowest PAPR is selected to transmit. Unlike the conventional method, it can cut down the computational complexity because it does not require the transmission and demodulation process of side information about the phase rotation. Furthermore, if this method is made up in parallel configuration, it can solve the time delay problem so that it can be processed in real time processing. This proposed method is compared with the conventional selected mapping(SLM) technique. We find out the PAPR reduction performance and BER when the number of control tone is 6 and nonlinear HPA is considered.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.217-230
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• 2012

This paper propose interacting test programming methods between test equipment and hardware unit to verify function and performance of the hardware unit under test. Proposed test program can minimizes the risk of failures when the unit is mounted on the aircraft by testing and verifying the unit under the worst stress condition. Also, Object oriented design using UML make it easy to apply in other equipments. Test program consists of architecture package and hardware package. Architecture package is in a role for system management, log analysis, message receiving and message analysis. Messages that are used by system management define messages for testing and defined messages is sent and received to test equipment through Ethernet. Hardware package is in a role for hardware management that is needed to be tested and is related to a system. Hardware to be tested is divided into internal test and transmission test. Internal test inspects hardware itself and reports the test results to the test equipment. Transmission test inspects communication device by sending or receiving data. All kinds of test is done in the worst condition of the test unit executing in parallel. Each device is tested at least 482 times and at most 15,003 times about one hour. Test program is utilized in hardware reliability test like as environmental test or EMI test.

• Journal of IKEEE
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• v.19 no.2
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• pp.168-175
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• 2015

In this paper, we propose FPGA design technique for rotating LED display device which is capable of displaying videos with the use of the afterimage effect. The proposed technique is made up of image data correction process based on inverse gamma correction and error diffusion, block interleaving process, and data serial output process. The data correction process based on inverse gamma correction and error diffusion is an image data correction step in which image data received are corrected by inverse gamma correction process to convert the data into linear brightness characteristics, and by error diffusion process to reduce the brightness reduction phenomenon in low-gray-level which is caused by inverse gamma correction. In the block interleaving process, the data of the frames entered transversely are first saved in accordance with entrance order, and then only the longitudinal image data are read. The data serial output process is applied to convert the parallel data in a rotating location into serial data and send them to LED Driver IC, in order to send data which will be displayed on high-speedy rotating LED Bar. To evaluate the accuracy of the proposed FPGA design technique, this paper used XC6SLX45-FG484, a Spartan 6 family of Xilinx, as FPGA, and ISE 14.5 as a design tool. According to the evaluation analysis, it was found that goal values were consistent with simulation values in terms of accurate operation of inverse gamma and error diffusion correction, block interleaving operation, and serialized operation of image data.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.2
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• pp.165-172
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• 2019

Using two or more coaxial lines, if one port is connected in series and the other port is connected in parallel, it can be implemented the wideband transmission line transformer(TLT). Because the wideband TLT utilizes the outer conductor of the coaxial line, it is difficult to predict the characteristics. In this paper, based on the analysis for the transfer characteristic(S21) according to the loss of the each line in ${\lambda}/4$-microstrip line TLT, the operating characteristic of the fabricated wideband 4:1 TLT using two $25{\Omega}$-coaxial lines is investigated. The fabricated wideband TLT shows the notch characteristic in which the transfer signal sharply decreases at ${\lambda}/4$ frequency of the coaxial line and has a value within -0.2dB of the transfer characteristic(S21) in $0.06{\sim}0.2{\lambda}$ frequency range of the coaxial line. This transfer characteristics(S21) can change the operating frequency range slightly and set the optimum transfer characteristic(S21) at the desired frequency by changing the length of the microstrip line.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.2B
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• pp.138-143
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• 2003

One of the important design issues for IP routers responsible for packet forwarding in computer networks is the route-lookup mechanism. For each incoming packet, IP routing requires that a router performs a longest-prefix-match address lookup in order to determine the next hop that the incoming packet should be forwarded to. In this paper, we present a new scheme which applies the hashing function for IP address lookup. In the proposed scheme, the forwarding table is composed of multiple SRAMs, and each SRAM represents an address lookup table in each prefix. Hashing function is applied in order to find out the matching entries from the address lookup tables in parallel, and the entry with the longest prefix match among them is selected. Simulation using the MAE-WEST router example shows that a large routing table with 37000 entries can be compacted to a forwarding table of 300 Kbytes in the proposed scheme. It is also shown that the proposed scheme achieves one route lookup every 1.93 memory accesses in average.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.230-238
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• 2005

An orthogonal frequency division multiplexing (OFDM) system consists of a number of independently modulated subcarriers and, thus, a high peak-to-average power ratio (PAR) can occur when the subcarriers are added coherently. The high PAR brings such disadvantages as an increased complexity of the analog-to-digital (ADC) and digital-to-analog (DAC) converters and a reduced efficiency of the radio frequency (RF) power amplifier. In this paper, we propose a novel PAR reduction scheme called selective mapping of partial tones (SMOPT). The SMOPT scheme has a reduced complexity, lower sensitivity to peak reduction tones (PRT) positions, and a shorter processing time as compared with the conventional tone reservation (TR) scheme. The performance of the SMOPT scheme is analyzed based on the IEEE 802.1la wireless local area network(WLAM) physical layer model. Numerical results show that the SMOPT scheme outperforms the TR scheme under various scenarios.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.1-9
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• 2012

Quantum-Inspired Evolutionary Algorithm(QEA) contains sufficient data-level parallelism to be naturally accelerated on GPUs. For an efficient reduction of execution time, however, careful task-mapping should be done to properly reflect the characteristics of CPU and GPU. Furthermore, when deciding which part of the application should run on GPU, we need to consider the data transfer between CPU and GPU memory spaces as well as the data-level parallelism. In addition, the usage of zero-copy host memory, proper choice of the execution configuration, and thread organization considering memory coalescing is important to further reduce the execution time. With all these techniques, we could run QEA 3.69 times faster on average in comparison with the multi-threading CPU for the case of 0-1 knapsack problem with 30,000 items.

• Journal of Digital Convergence
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• v.12 no.1
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• pp.379-388
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• 2014

We noted that substituting hard disk with high-performance storage device on SAN did not immediately result in getting high performance. Investigating the reason behind this leaded us to propose optimization schemes for high-performance storage system. We first got rid of the latency in the I/O process which is unsuitable for the high-performance storage device, added parallelism on the storage server, and applied temporal merge to Superhigh speed network protocol for improving the performance with small random I/O. The proposed scheme was implemented on the SAN with high-performance storage device and we verified that there were about 30% reduction on the I/O delay latency and 200% improvement on the storage bandwidth.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.52-62
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• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.