• Journal of the Institute of Convergence Signal Processing
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• v.2 no.4
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• pp.65-70
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• 2001

In this paper a new scheme combining the turbo coder with parallel interference canceller, which effectively mitigates the effects of multiple access interferences and Ralyeigh fades in the DS-CDAM mobile communication systems is proposed Using the Monte-Carlo simulation, the performance of this scheme in terms of the number of users and signal to noise ration under AWGN and Ralyeigh fading environment is analyzed. The results of simulations show that the proposed scheme outperforms conventional CDMA receiver systems over Rayleigh fading as well as AWGN.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2C
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• pp.181-186
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• 2004

Recently, there has been intensive focus on Turbo Product Codes(TPCs) which have low decoding complexity and achieve near-optimum performances at high code-rate. This paper present a parallel algorithm of turbo product codes enable simultaneous decoding of row and column. The row and column decoders operate in parallel and update each other after row and column has been decoded. simulation results show that the performance of proposed parallel turbo code is almost the same as that conventional scheme for several turbo product codes.

• Information and Communications Magazine
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• v.24 no.4
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• pp.83-94
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• 2007

터보 부호는 AWGN 환경에서 비교적 간단한 복호 알고리즘을 가지면서 낮은 신호대 잡음비에서 뛰어난 에러 성능을 보이는 채널부호이다. 터보 부호는 기본적으로 길쌈 부호를 병렬 연접하는 방식으로, 두 개 이상의 구성 부호화기에 같은 시퀀스의 서로 다른 배열을 적용하는 것이다. 본 논고에서는 터보 부호화 및 복호화의 기본 원리에 대하여 설명하고, 이를 여러 형태의 무선 채널에 적용하는 기술에 대하여 언급하고자 한다. 그리고 연구 방향에 대하여 간략히 제시하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.269-280
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• 1996

We proposed a symbolic substitution method based on an optical correlator for an optical parallel addition. In the proposed symbolic substitution method, we used redundant binary number of the symbolic substitution rules as a number system and chose MAC3E filter which had very low sidelobes and good correlation peak compared with SDF filter as the optical correlation filter. We encoeded input numbers property to increase the discrimination capability and divided inpt patterns into 5 groups of the same addition results to minimize the number of symbolic substitution rules. Through the computer simulation, we confirmed the proposed method was suitable to implement the optical parallel adder.

• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1620-1632
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• 1998

This paper presents a fast parallel algorithm for volume rendering and its implementation using C language and MPI MasPar Programming Language) on the 4,096 processor MasPar MP-2 machine. This parallel algorithm is a parallelization hased on the Lacroute' s sequential shear - warp algorithm currently acknowledged to be the fastest sequential volume rendering algorithm. This algorithm reduces communication overheads by using the sheared space partition scheme and the load balancing technique using load estimates from the previous iteration, and the number of voxels to be processed by using the run-length encoded volume data structure.Actual performance is 3 to 4 frames/second on the human hrain scan dataset of $128\times128\times128$ voxels. Because of the scalability of this algorithm, performance of ]2-16 frames/sc.'cond is expected on the 16,384 processor MasPar MP-2 machine. It is expected that implementation on more current SIMD or MIMD architectures would provide 3O~60 frames/second on large volumes.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.93-96
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decode. is parameterized for the code rates 1/2, 1/3 and constraint lengths 7, 9, thus it has four operation modes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.7
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• pp.13-23
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• 2009

In this paper, the network performance of a turbo coded optical code division multiple access (CDMA) system with cross-layer, which is between physical and network layers, concept is analyzed and simulated. We consider physical and MAC layers in a cross-layer concept. An intensity-modulated/direct-detection (IM/DD) optical system employing pulse position modulation (PPM) is considered. In order to increase the system performance, turbo codes composed of parallel concatenated convolutional codes (PCCCs) is utilized. The network performance is evaluated in terms of bit error probability (BEP). From the simulation results, it is demonstrated that turbo coding offers considerable coding gain with reasonable encoding and decoding complexity. Also, it is confirmed that the performance of such an optical CDMA network can be substantially improved by increasing e interleaver length and e number of iterations in e decoding process. The results of this paper can be applied to implement the indoor optical wireless LANs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.185-192
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• 1999

In this paper. for $\pi$/4 and $\pi$/8 PSK. we proposed to condition to obtain coding gain increasing states, by design encoder of analytical method with minimal complexity in limited bandwidth and power channels. In order to improve the bit error rate(BER), comparing Ungerboeck designed the TCM. we propose MTCM(Multiple trellis-coded modulation) with multiplicity(k＝2), by optimum encoder design. By design encoder of analytical method. the trellis encoder can be minimal complexity and the decoder be used Viterbi decoder(MLSE). When compared to the TCM and MTCM with AWGN channels. the condition of performance enhancement of the MTCM with multiplicity(k＝2) is the case of parallel transition in TCM systems. without alternating data transmission rate in bandwidth and power limited channels.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2015.11a
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• pp.149-151
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• 2015

본 논문에서는 4K UHD 입력 영상에 대해 각 프레임을 다중 슬라이스로 분할하고, 이를 병렬 처리를 통해 실시간으로 부호화를 수행하는 소프트웨어 기반 HEVC 인코더의 율 제어 방법에 관한 연구이다. 이를 위하여 HEVC 가 지원하는 슬라이스를 적용하여 프레임을 독립적인 다중 슬라이스로 분할하였고, 각각의 슬라이스에 대해서는 기존에 제안된 몇 가지의 율 제어 방법을 개선하여 적용하였다. 본 논문에서는 다중 슬라이스에 각각 독립적으로 적용한 율 제어 방법에 대한 실험 결과를 통해 제안된 율 제어 방법의 안정성을 확인하고, 향후 연구로서 각 슬라이스의 출력 비트율을 예측하고 다중 슬라이스에 효과적으로 할당하는 방법과 이를 통한 주관적 화질을 향상 하는 방법에 대해 논한다.