• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.2
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• pp.69-80
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• 2002

In this paper, signed-rank based nonparametric detectors are used for direct sequence code division multiple access pseudo-noise code acquisition systems in frequency-selective Rician fading channels. We first derive the locally optimum rank detector, and then propose the locally suboptimum rank (LSR) and k-th order modified signed-rank (MSRk) detectors using approximate score functions. We compare the serial and hybrid parallel double-dwell schemes using the LSR and MSRk detectors with those using the conventional squared-sum (SS) using the cell averaging constant false alarm rate processor and modified sign detectors. From the simulation results, it is shown that the LSR and MSRk detectors perform better than the SS detector using the cell averaging constant false alarm rate processor.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.114-123
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• 2014

Vehicle Black Box (Event Data Recorder EDR) only recognizes the general surrounding environments of load. In addition, general EDR is difficult to recognize the images of a sudden illumination change. It appears that the lens is being a severe distortion. Therefore, general EDR does not provide the clues of the circumstances of the accident. To solve this problem, we estimate the value of Normalized Luminance Descriptor(NLD) and Normalized Contrast Descriptor(NCD). Illumination change is corrected using Normalized Image Quality(NIQ). Second, we are corrected lens distortion using model of Field Of View(FOV) based on designed method of fisheye lens. As a result, we propose integration algorithm of two methods that correct distortions of images using each Gamma Correction and Lens Correction in parallel.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.6
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• pp.1-11
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• 2004

Modern processors achieve high performance exploiting avaliable Instruction Level Parallelism(ILP) by using speculative technique such as branch prediction. Traditionally, branch direction can be predicted at very high accuracy by 2-level predictor, and branch target address is predicted by Branch Target Buffer(BTB). Except for indirect branch, each of the branch has the unique target, so its prediction is very accurate via BTB. But because indirect branch has dynamically polymorphic target, indirect branch target prediction is very difficult. In general, the technique of branch direction prediction is applied to indirect branch target prediction, and much better accuracy than traditional BTB is obtained for indirect branch. We present a new indirect branch target prediction scheme which combines a indirect branch instruction with its data dependent register of the instruction executed earlier than the branch. The result of SPEC benchmark simulation which are obtained on SimpleScalar simulator shows that the proposed predictor obtains the most perfect prediction accuracy than any other existing scheme.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.132-135
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.781-788
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• 2017

This paper proposes a new algorithm for comparing amplitude between multiple digital input signals and its digital logic architecture. After simultaneously comparing multiple inputs, the proposed algorithm can provide the information of the largest (or smallest) value among them by using a simple digital logic function. The drawback of the method is to increase hardware resource. To overcome this we propose a reuse method of the overlapped logic operation. The proposed method focuses on enhancing the operational clock frequency, in other words decreasing combinational delay time. After implementing the comparing method with HDL (hardware description language), we experiment on it with environment of Cyclone III EP3C40F324A7 FPGA of Altera Inc. In case of 4 input signals, it can increase the operational speed as mush as 1.66 times with 1.20 times the hardware resource. In case of 8, it can also have 2.29 times the clock frequency and 2.15 times the hardware resource.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.190-196
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• 2014

This paper proposes a mobile-optimized pedestrian detection method using Cascade of HOG(Histograms of Oriented Gradients) for ADAS(Advanced Driver Assistance System) on smartphones. In order to use the limited resource of mobile platforms efficiently, the method is implemented by the OpenCL(Open Computing Language) library, and its processing time is reduced in the following two aspects. Firstly, the method sets a program build option specifically and adjusts work group sizes as variety of kernels in the host code. Secondly, it utilizes local memory and a LUT(Look-Up Table) in the kernel code to accelerate the program. For performance evaluation, the developed algorithm is compared with the mobile CPU-based OpenCV(Open Computer Vision) for Android function. The experimental results show that the processing speed is 25% faster than the OpenCV hogcascade.

• Journal of the Korean Society for Nondestructive Testing
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• v.17 no.3
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• pp.162-173
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• 1997

Automatic on-line surface inspection systems have been applied for monitoring a quality of steel strip surfaces. One of the important issues in this application is the performance of on-line defect classifiers. Rule-based classification table methods which are conventionally used for this purpose have been suffered from their low performances. In this work, probabilistic neural networks and the enhanced classification tables which are newly proposed here are applied as alternative on-line classifiers to identify types of surface defects on cold rolled strips. Probabilistic neural networks have shown very excellent performance for classification of surface defects.

• The Korean Journal of Applied Statistics
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• v.29 no.6
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• pp.1077-1094
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• 2016

Apache Spark is a fast and general-purpose cluster computing package. It provides a new abstraction named resilient distributed dataset, which is capable of support for fault tolerance while keeping data in memory. This type of abstraction results in a significant speedup compared to legacy large-scale data framework, MapReduce. In particular, Spark framework is suitable for iterative machine learning applications such as logistic regression and K-means clustering, and interactive data querying. Spark also supports high level libraries for various applications such as machine learning, streaming data processing, database querying and graph data mining thanks to its versatility. In this work, we introduce the concept and programming model of Spark as well as show some implementations of simple statistical computing applications. We also review the machine learning package MLlib, and the R language interface SparkR.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.12
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• pp.41-50
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• 1999

In this paper, the new VLSI architecture of a reconstruction filter for morphological image segmentation is proposed. The filter, based on the $h_{max}$ operation, simplifies the interior of each region while preserving the boundary information. The proposed architecture adopts a partitioned memory structure and an efficient image scanning strategy to reduce the operations. The proposed memory partitioning scheme makes it possible that every data required for processing can be read from each memory at a time, resulting in parallel data processing. By the extended connectivity consideration, the operation is much decreased because more simplification is achieved in scanning stage. The selective raster scan strategy endows the satisfactory noise removal capability with negligible hardware complexity increase. The proposed architecture is designed using VHDL, and functional evaluation is performed by the CAD tool, Mentor. The experiment results show that the proposed architecture can simplify image profile with less than 18% operations of the conventional method.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.45-53
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• 2015

Adaptive support-weight based algorithm can produce better disparity map compared to generic area-based algorithms and also can be implemented as a realtime system. In this paper, we propose a realtime system based on geodesic support-weight which performs better segmentation of objects in the window. The data scheduling is analyzed for efficient hardware design and better performance and the parallel architecture for weight update which takes the longest delay is proposed. The exponential function is efficiently designed using a simple step function by careful error analysis. The proposed architecture is designed with verilogHDL and synthesized using Donbu Hitek 0.18um standard cell library. The proposed system shows 2.22% of error rate and can run up to 260Mhz (25fps) operation frequency with 182K gates.