• Journal of the Korea Computer Industry Society
• /
• v.7 no.3
• /
• pp.185-190
• /
• 2006

In this paper, a simple parallel compiler using of Parafrase II is presented. This is a new general method the extracting parallelism in order to parallel processing effectively in nested loop. For this, the source program of Parafrase II parallel compiler is analyzed and implemented. Moreover, this method can be applicable where the dependency relation is both uniform and non-uniform in distance.

• Proceedings of the Korean Information Science Society Conference
• /
• 2000.04a
• /
• pp.657-659
• /
• 2000

네트워크 처리속도의 증가로 네트워크 컴퓨팅 환경에서의 작업이 늘고 있다. 플랫폼 독립성이라는 특성을 내세운 자바는 일반적인 이 기종간의 네트워크에서의 프로그래밍 언어로 많이 이용되고 있다. 그리고 이러한 네트워크 컴퓨팅 환경에서 병렬 프로그램 디버깅의 어려움으로 인해 자바 병렬 프로그램을 위한 디버거의 필요성이 요구되고 있다. 기존의 디버거들은 이런 병렬 환경에서의 디버깅을 각 프로세서에 하나의 순차디버거를 붙인 디버깅 환경을 제공한다. 그러나 병렬 프로그램은 순차프로그램과 다른 재실행시의 비결정적인 특성을 가지고 있음으로 일반적인 순차 디버거를 이용한 디버깅은 의미가 없다. 본 논문에서는 자바로 구현된 네트워크 컴퓨터(JaNeC)에서 병렬프로그램을 디버기하기 위하여 재실행 시 실행 순서를 보장하는 자바 디버거를 소개한다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2006.11a
• /
• pp.161-164
• /
• 2006

인터넷이 발전하면서 웹에는 같은 내용을 다양한 언어로 표현한 문서들이 많이 존재한다. 이와 같은 웹 문서의 성질을 이용하여, 이 논문은 웹으로부터 수집된 병렬문서(parallel document)를 이용하여 한영 병렬말뭉치 구축 시스템을 설계하고 구현한다. 이 논문에서 구축과정을 요약하면 다음과 같다. 첫째, 웹 문서수집기를 이용해서 웹으로부터 한영 웹문서(html 문서)를 각각 수집한다. 둘째, 수집된 각 언어의 웹 문서에서 불필요한 내용(태그와 광고 문구 등)을 제거하여 문장을 추출하고, 추출된 문장을 단락단위로 정렬한다. 셋째, 단락단위로 정렬된 문서를 문장정렬(sentence alignment) 방법을 이용해서 문장을 정렬한다. 끝으로 정렬된 병렬문장을 단어 단위로 분리하여 병렬말뭉치를 구축한다. 이와 같은 방법으로 이 논문에서는 약 42만 5천 문장의 한영 병렬말뭉치를 구축하였다.

• Journal of Advanced Navigation Technology
• /
• v.21 no.5
• /
• pp.485-490
• /
• 2017

In this paper, we propose a technique for high speed removal of sea-fog using a graphic processor. This technique uses a host processor(CPU) and several graphics processors(GPU) capable of parallel processing to remove sea-fog from the input image. In the process of removing sea-fog, the dark channel extraction, the maximum brightness channel extraction, and the calculation of the transmission are performed by the host processor, and the process of refining the transmission by applying the bidirectional filter is performed in parallel through the graphic processor. To verify the proposed parallel processing method, three NVIDIA GTX 1070 GPUs were used to construct the verification environment. As a result, it takes about 140ms when implemented with one graphics processor, and 26ms when implemented using OpenMP and multiple GPGPUs. The proposed a parallel processing algorithm based on the graphics processor unit can be used for safe navigation, port control and monitoring system.

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.10
• /
• pp.2544-2552
• /
• 1997

This paper presents three multiprocess models for parallel protocol implementation, that is, (1)channel communication model, (2)fork-join model, and (3)event polling model. For the specification of parallelism for each model, a parallel programming language, Par. C System, is used. to measure the performance of multiprocess models, we implemented the Internet Protocol Suite(IPS) Internet Protocol (IP) for each model by writing the parallel language on the Transputer. After decomposing the IP functions into two parts, that is, the sending side and the receiving side, the parallelism in both sides is exploited in the form of Multiple Instruction Single Data (MISD). Three models are evaluated and compared on the basis of various run-time overheads, such as an event sending via channels in the parallel channel communication model, process creating in the fork-join model and context switching in the event polling model, at the sending side and the receiving side. The event polling model has lower processing delays as about 77% and 9% in comparison with the channel communication model and the fork-join model at the sending side, respectively. At the receiving side, the fork-join model has lower processing delays as about 55% and 107% in comparison with the channel communication model and the event polling model, respectively.

• Journal of Internet Computing and Services
• /
• v.15 no.2
• /
• pp.41-47
• /
• 2014

In this paper, we implemented a CUDA Fortran parallel program to run the CFD_NIMR model on GP-GPU's, which simulates air diffusion on urban terrains. A GP-GPU is graphic processing unit in the form of a PCI card, and a general calculation accelerator to perform a large amount of high speed calculations with low cost and electric power. The GP-GPU gives performance enhancement of speed by 15 times to compare the Nvidia Tesla C1060 GPU with Intel XEON 2.0 GHz CPU. In addition, the program on a GP-GPU shows efficient performance compared to an MPI parallel program on multiple CPU's. It is expected that a proposed programming method on the GP-GPU parallel program can be used for numerical models with a similar structure.

• Journal of the Korea Computer Graphics Society
• /
• v.25 no.3
• /
• pp.55-63
• /
• 2019

Recently, the GPU computing method has been utilized to improve the performance of the physics simulation field. In particular, in the case of a deformed object simulation requiring a large amount of computation, a GPU-based parallel processing algorithm is required to guarantee real-time performance. We have studied the parallel structure design method to improve the performance of the mass spring simulation method which is one of the methods of implementing the deformation object simulation. We used OpenGL's GLSL, a graphics library that allows direct access to the GPU, and implemented the GPGPU environment using an independent pipeline, the compute shader. In order to verify the effectiveness of the parallel structure design method, the mass - spring system was implemented based on CPU and GPU. Experimental results show that the proposed method improves computation speed by about 6,000% compared to the CPU Environment. It is expected that the lightweight simulation technology can be effectively applied to the augmented reality and the virtual reality field by using the design method proposed later in this research.

• 전기의세계
• /
• v.38 no.1
• /
• pp.31-38
• /
• 1989

• Journal of the Korea Society of Computer and Information
• /
• v.16 no.10
• /
• pp.11-21
• /
• 2011

This paper introduces an SIMD(Single Instruction Multiple Data) based parallel processor that efficiently processes massive data inherent in multimedia. In addition, this paper implements MMX(MultiMedia eXtension)-type instructions on the data parallel processor and evaluates and analyzes the performance of the MMX-type instructions. The reference data parallel processor consists of 16 processors each of which has a 32-bit datapath. Experimental results for a JPEG compression application with a 1280x1024 pixel image indicate that MMX-type instructions achieves a 50% performance improvement over the baseline instructions on the same data parallel architecture. In addition, MMX-type instructions achieves 100% and 51% improvements over the baseline instructions in energy efficiency and area efficiency, respectively. These results demonstrate that multimedia specific instructions including MMX-type have potentials for widely used many-core GPU(Graphics Processing Unit) and any types of parallel processors.

• Journal of the Korea Society of Computer and Information
• /
• v.16 no.5
• /
• pp.1-11
• /
• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements (PEs) and operates on a 3-stage pipelining. Experimental results indicated that the proposed parallel processor outperforms conventional parallel processors in terms of performance. In addition, our proposed parallel processor outperforms commercial high-performance TI C6416 DSP in terms of performance (1.4-31.4x better) and energy efficiency (5.9-8.1x better) with same 130nm technology and 720 clock frequency. The proposed parallel processor was developed with verilog HDL and verified with a FPGA prototype system.