• Transactions of the Korean Society of Automotive Engineers
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• v.2 no.1
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• pp.106-115
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• 1994

A parallel integration approach is proposed for real-time simulation of controlled mechanical systems. The proposed approach, which employs the dual-rate integration method in a parallel computing environment, is developed to deal with stiffness and high frequency characteristics of the controlled mechanical systems effectively. Numerical experiments are performed to demonstrate the effectiveness of the approach in shared memory multiprocessors, Alliant FX/8 and Alliant FX/80.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.995-1001
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• 2005

Implicit Integration has become a standard approach to efficient cloth animation, and it guarantees the stability of the system so that large steps can be used. Therefore, it is regarded as the best method for the real-time or interactive animation of cloth. Since the implicit method was introduced for stable cloth animation, various cloth animation techniques based on the method have been proposed. It is now possible to generate the real-time animation of cloth model with thousands of mass-point in general PC environments. Although the implicit method guarantees the stability, the implementation of the implicit method is generally more difficult than that of the explicit method. Even worse, it is very difficult to parallelize the computation process of the implicit method. The cloth animation with implicit method can be formalized as a linear system solving. In this paper we propose an stable and efficient cloth animation techniques based on the implicit method. The proposed method can be easily parallelized. Self-collision is another important issue in cloth animation, we also propose an efficient self-collision avoidance techniques.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2009.05a
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• pp.196-199
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• 2009

높아지는 Graphic Processing Unit (GPU)의 연산 성능과 GPU에서의 범용 프로그래밍을 위한 개발 환경의 개발, 보급으로 인해 GPU를 일반연산에 활용하는 연구가 활발히 진행되고 있다. 이와같이 일반 연산에 활용되고 있는 GPU로 nVidia Tesla와 AMD/ATI의 FireStream 들이 있다. 특수목적 연산 장치인 GPU를 일반 연산을 위해 프로그래밍하기 위해서는 그에 맞는 프로그램 개발 환경이 필요한데 nVidia에서 개발한 CUDA (Compute Unified Device Architecture) 환경은 자사의 GPU 프로그램 개발을 위해 제공되는 개발 환경이다. CUDA 개발 환경은 nVidia GPU 프로그래밍 뿐만 아니라 차세대 이종 병렬 프로그램 개발 환경의 공개 표준으로 논의되고 있는 OpenCL (Open Computing Language) 와 유사한 특징을 보일 것으로 예상되기 때문에 그 중요성은 특정 GPU 에만 국한되지 않는다. 본 논문에서는 경로 적분 몬테 카를로 (Path Integral Monte Carlo) 방법을 CUDA 개발 환경을 사용하여 nVidia GPU 상에서 병렬화한 결과를 제시하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2016.04a
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• pp.59-60
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• 2016

본 논문에서는 고성능 병렬 계산 장치로 주목받고 있는 GPU를 CPU와 동시에 병렬로 사용한 계산 성능을 분석하였다. 성능 분석을 위하여 원주율(${\pi}$)을 적분으로 계산하는 CUDA 프로그램을 사용하였으며, 전체 계산을 GPU 대비 CPU 계산 부분으로 할당하여 성능을 분석하였다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.8 no.2
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• pp.24-33
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• 1971

A noble method of delta modulation by means of pair transistor circuit having negative resistance charcteristic is presented. An RC parallel circuit is inserted between two eiuitter tarminals of the pair transistor circuit, and their emitters are driven by a square pulsed current source. Basically this is a relaxation oscillator circuit. But when the value of capacitors and resistanc R, and the pulse height of driving source are properly chosen, the RC parallel circuit apparently functions as integrating circuit of driviving pulses. Compared with the integrated voltage of capacitor C, a signal input voltatage supplied in series with RC parallel circuit between two emitters makes on or off either of the pair transistors. as the result, one bit pulse is sent out from the coupling resistance terminal of conducted transistor. The circuit diagram used for this experiment is presented, it i% composed with simple mod ulster circuit, differential amplifier and pulse shaping amplifier, The characteristics of the components of this ciruit are discussed, and especially quantumized noise in this delta modulation system is discussed in order to improve the signal to noise ratio which has a close relation with circut constants, quantumized voltage, pulse height and width of driving current source.

• Journal of Institute of Control, Robotics and Systems
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• v.3 no.2
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• pp.139-148
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• 1997

본 논문에서는 비선형 마찰이 존재하는 조준경 안정화 시스템에 대해서 마찰력 보상과 성능개선을 위한 신경망제어기의 설계방법을 제시한다. 제안한 신경망제어기는 비례, 적분, 진상(PI/LEAD) 제어기와 신경회로망과의 병렬로 구성되며, 제어 목적은 비선형 마찰과 외란이 존재하여도 안정거울의 각속도 추적성능과 안정화 성능의 향상에 있다. 신경회로망의 입력으로 안정거울의 각속도 추적오차와 추적오차의 적분, 제어입력이 필터를 통과한 신호가 사용되며, 신경호로망은 간접학습구조에 의해 학습된다. 조준경 시스템의 비선형 마찰력인 쿨롱마찰력의 크기가 외부환경에 따라 변하는 경우와 시스템으로 외란이 인가되는 경우에 대하여도 제안한 병렬제어기는 기존의 PI/LEAD 제어기보다 추적과 안정화 성능면에서 우수함을 컴퓨터 모의 실험으로 확인한다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.497-500
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• 1995

In this paper, a program for real time simulation of a vehicle is developed. The program uses relative coordinates and BEF(Backward Difference Formula) numerical integration method. Numerical tests showed that the proposed implicit method is more stable in carring out the numerical integration for vehicl dynamics than the explicit method. Hardware requirements for real time simulation are suggested. Algorithms of parallel processing is developed with DSP (digital signal processor).

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.91-93
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• 2004

정확한 $\pi$값의 계산은 자연과학의 여러 분야에 도움을 준다 이와 같이 $\pi$값을 계산하는 여러 가지 방법이 제안되어 있으며 널리 사용되고 있으나, 본 논문에서는 MPI 라이브러리를 활용한 $\pi$값 계산의 병렬화 알고리즘을 소개한다. tan$^{-1}$($\chi$)의 정의를 이용하는 $\pi$값 계산 방법은 다항식의 계산과정에서 각 항(term)들의 종속성으로 인하여 병렬화 수행이 힘든 단점이 있다. 본 논문에서는 tan$^{-1}$($\chi$)를 맥클로린 수열(Maclaurin Series)을 통하여 다항함수로 표현하고, 병렬화 수행에 적합한 적분형태로 변형한다. 따라서. MPI 환경에서 수행하기 적합한 $\pi$값 계산의 병렬화 알고리즘을 제안하고 8노드 클러스터 환경에서 성능을 비교해본다. 또한, 직렬화된 방법에 대한 성능향상(speedup)을 측정한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2B
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• pp.125-136
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• 2002

It is very important to acquire the synchronization in a intercell asynchronous WCDMA system, and it is carried out through the three-step cell search process. The cell search can operate in a stepwise parallel manner, where each step works in pipelined operation, to reduce the cell search time. In case that the execution time is set to be the same in each step, excessive accumulations will be caused in both step 1 and step 3, because step 2 should take at least one frame for its processing. In general, the effect of post-detection integration becomes saturated as the number of the accumulations increases. Therefore, the stepwise parallel scheme does not give much enhancement. In this paper, the performance of the stepwise parallel processing for cell search in WCDMA system is analyzed over Rayleigh fading channels. Through the analysis, the effect of cell search parameters such as the number of accumulations in each step and the power ratio allocated among channels is investigated. In addition, the performance of the stepwise parallel cell search is improved by adjusting the execution time appropriately for each step and is compared with that of the conventional stepwise serial processing.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.75-81
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• 2014

The integral image is the sum of input image pixel values. It is mainly used to speed up processing of a box filter operation, such as Haar-like features. However, large memory for integral image data can be an obstacle on an embedded hardware environment with limited memory resources. Therefore, an efficient method to store the integral image is necessary. In this paper, we propose a memory size reduction hardware design for integral image. The hardware design is used two methods. It is the new integral image memory and modulo calculation for reducing integral image data. The new integral image memory has additional calculation overhead, but it is not obstacle in hardware environment that parallel processing is possible. In the Xilinx Virtex5-LX330T targeted experimental result, integral image memory can be reduced by 50% on a $640{\times}480$ 8-bit gray-scale input image.