• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.654-654
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• 2004

본 논문에서는 이산웨이블렛 변환을 이용한 영상 압축 프로세서를 하드웨어로 구현하였다. 웨이블렛 변환을 위하여 필터뱅크 및 피라미드 알고리즘을 이용하였고 각 필터들은 FIR 필터로 구현하였다. 병렬구조로 이루어져 동일 클럭 싸이클에서 하이패스와 로패스를 동시에 수행함으로써 속도를 향상시킬 뿐 아니라 QMF 특성을 이용하여 DWT 연산에 필요한 승산기의 수를 절반으로 줄임으로써 하드웨어 크기를 줄이고 이용효율 또한 높일 수 있다. 다중 해상도 분해 시 필요한 메모리 컨트롤러를 하드웨어로 구현하여 DWT 계산이 수행되므로 이 융자는 단순한 파라메터 입력만으로 효과적인 압축율을 얻을 수 있도록 구조적으로 설계하였다. 실시간 영상압축 프로세서의 성능 예측을 위하여 MATLAB을 통하여 시뮬레이션 하였고, VHDL을 이용하여 각 모듈들을 설계하였다. 설계한 영상압축기는 Leonaro-Spectrum에서 합성하였고, ALTERA FLEX10KE(EPF10K100 EFC256) FPGA에 이식하여 하드웨어적으로 동작을 검증하였다. 설계된 부호화기는 512×512 Woman 영상에 대하여 33㏈의 PSNR값을 갖는다. 그리고 설계된 프로세서를 FPGA 구현 시 35㎒에서 정상적으로 동작한다.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2617-2620
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• 2003

This paper presents the construction algorithm of the irreducible polynomial which needs to multiply over GF(2$\^$m/) and the flow chart representing the proposed algorithm has been proposed. And also, we get the degree from the value of xm＋k formation to the value of k = 7 using the proposed flow chart. The multiplier circuit has been implemented by using the proposed irreducible polynomial generation(IPG) algorithm in this paper, and we compared the proposed circuit with the conventional one. In the case of k = 7, one AND gate and five Ex-or gates are needed as the delay time for the irreducible polynomial in the proposed algorithm, but seven AND gates and sever Ex-or gates in the conventional one. As a result, the proposed algorithm shows the improved performance on the delay time.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.771-774
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• 1998

In this paper proposes a new bit-parallel structure for a multiplier over GF((Pn)m), with k-nm. Mastrovito Multiplier, Karatsuba-ofman algorithm are applied to the multiplication of polynomials over GF(2n). This operation has a complexity of order O(k log p3) under certain constrains regardig k. A complete set of primitive field polynomials for composite fields is provided which perform modulo reduction with low complexity. As a result, multiplier for fields GF(Pk) with low gate counts and low delays are constructed. The architectures are highly modular and thus well suited for VLSI implementation.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.741-744
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• 1999

In this paper, We represent a low complexity of parallel canonical basis multiplier for GF( q$^{n}$ ), ( q＞ 2). The Mastrovito multiplier is investigated and applied to multiplication in GF(q$^{n}$ ), GF(q$^{n}$ ) is different with GF(2$^{n}$ ), when MVL is applied to finite field. If q is larger than 2, inverse should be considered. Optimized irreducible polynomial can reduce number of operation. In this paper we describe a method for choosing optimized irreducible polynomial and modularizing recursive polynomial operation. A optimized irreducible polynomial is provided which perform modulo reduction with low complexity. As a result, multiplier for fields GF(q$^{n}$ ) with low gate counts. and low delays are constructed. The architectures are highly modular and thus well suited for VLSI implementation.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.282-284
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• 1988

In this paper, a method for constructing parallel-in, parallel-out multipliers in GF($2^{m}$) is presented. The proposed system is composed of two operational parts by using shift register. One is a multiplicative arithmetical operation part capable of the multiplicative arithmetic and modulo 2 operation to all product terms with the same degree. And the other is an irreducible polynomial operation part to outputs from the multiplicative arithmetical operation part. Since the total hardware is linearly m dependant to an GF($2^{m}$), this system has a reasonable merit when m increases. And also this system is suited for VLSI implementation due to simple, regular, and concurrent properties.

• The Journal of the Acoustical Society of Korea
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• v.12 no.1E
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• pp.39-47
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• 1993

2-Dimension IIR 디지털 필터를 시스토릭 어레이 구조로 실현하는 방법을 보였다. 시스토릭 어레이는 1-D IIR 디지털 필터로 부분 실현한 후 종속연결하여 구현하였다. 부분 실현한 시스토릭 어레이의 종속 연결은 신호 지연에 사용되는 요소를 감소 시킨다. 여기서 1-D 시스토릭 어레이는 local communication 접근에 의해 DG를 설계한후 SFG로의 사상을 통해 유도하였다. 유도된 구조는 매우 간단하며, 입력 샘플이 공급되어지면 매 샘플링 기간마다 새로운 출력을 얻는 매우 높은 데이터 처리율을 갖는다. 2-Dimension IIR 디지털 필터를 시스토릭 어레이로 실현함으로써 규칙적이고, modularity, local interconnection, 높은 농기형 다중처리의 특징을 갖기 때문에 VLSI 실현에 매우 적합하다. 또한 PE셀의 승산기 설계에서는 modified Booth's 알고리즘과 Ling's 알고리즘에 기초를 두고 고도의 병렬처리를 행할수 있도록 설계하였다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.10 s.340
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• pp.17-24
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• 2005

This paper propose a new generation method of GRM coefficients using the circulation property of polarity over GF(3). The general method to derive GRM coefficients are obtain the filled polarity of GRM coefficients using RM expansion and expand it for the polarities. Since the general method has many operations when the number of the variables are incremented. Proposed method in this paper simplifies the generation procedure and reduces a number of operators compare to parallel type because of the cyclic property of polarity. Comparing to the proposed papers, the proposed method use only adders without multiplier. So it improves the complexity of the system with efficient composition of the circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.493-502
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• 2001

This paper propose a new built-in current sensor(BICS) for current testing that has some advantages compared with conventional logic testing. The designed BICS detects the fault in circuit under test (CUT) and makes a Pass/Fail signal by comparison between CUT current and duplicated inverter current. The proposed circuit consists of a differential amplifier, a comparator and a inverter. It requires 10 MOSFETs and 3 inverters. Since the designed BICS do not require the extra clock, the added extra pin is only one output pin. The mode selection is not used in this circuit. Therefore we can apply the circuit to on-line testing. The validity and effectiveness are verified through the HSPICE simulation of circuits with defects. When CUT is a 8$\times$8 parallel multiplier, area overhead of the BICS is about 4.34%.