• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.813-814
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• 2013

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.65-70
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• 2004

The SOC(System on Chip) testing has required the core re-use methodology and the efficiency of test method because of increase of its cost. The goal of SOC testing is to minimize the testing time, area overhead, and power consumption during testing. Prior research has concentrated on only one aspect of the test core wrapper design problem at a test time. Our research is concentrated on optimization of test time and area overhead for the core test wrapper, which is one of the important elements for SOC test architecture. In this paper, we propose an efficient wrapper design algorithm that improves on earlier approaches by also reducing the TAM(Test Access Mechanism) width required to achieve these lower testing times.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.87-95
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• 2004

This paper proposes a new test data compression/decompression method for SoC(Systems-on-a-Chip). The method is based on analyzing the factors that influence test parameters: compression ratio and hardware overhead. To improve compression ratio, the proposed method is based on Modified Statistical Coding (MSC) and Input Reduction (IR) scheme, as well as a novel mapping and reordering algorithm proposed in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.1
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• pp.235-244
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• 1999

This Paper proposes a new compaction algorithm for IDDQ testing in CMOS Circuits. A primary test pattern is generated by the primitive fault pattern which is able to detect GOS(gate-oxide short) and the bridging faults in an internal primitive gate. The new algorithm can reduce the number of the test vectors by decreasing the don't care(X) in the primary test pattern. The controllability of random number is used on processing of the backtrace together four ones of heuristics. The simulation results for the ISCAS-85 benchmark circuits show that the test vector reduction is more than 45% for the large circuits on the average compared to static compaction algorithms.

• Proceedings of the Korea Water Resources Association Conference
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• 2021.06a
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• pp.105-105
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• 2021

본 연구에서는 2차원 비선형 천수모형과 수심평균된 스칼라 이송모형을 해석하는 수치모형에 대해 기술하였다. 수치모형의 정확성을 보장함과 동시에 안정성을 높이기 위해 유한체적법, 플럭스 재구성 및 minmod 제한자를 사용하였다. 비선형 천수방정식의 이송항과 바닥 경사항은 계산된 수심의 양수 보존과 흐름의 정상 상태를 보장하기 위한 second order well-balanced positivity preserving central-upwind method를 이용하여 수치적으로 이산화되었다. 마찬가지로, 이송-확산 방정식 내 이송항은 동일한 2차 풍상차분법을 통해 수치적으로 풀이하였다. 격자점 경계면에서의 불연속으로 인한 수치진동을 방지하기 위해 이송항의 계산에 포함된 보존항의 차이로 인해 발생하는 스칼라의 수치확산을 최소화하기 위해 무차원의 비소산함수를 도입하였다. 또한, 확산항은 유한차분법을 이용하여 이산화하였다. 제안된 수치모형은 시간미분항의 계산을 위해 오일러 기법을 적용하여 계산된 수심 및 스칼라의 양수 보존여부와 함께 정지된 흐름의 정상 상태의 보존여부를 확인하였다. 제안된 수치모형의 해석 정확성을 평가하기 위해 1, 2차원 공간 내 다양한 흐름 조건에서의 해석해를 이용한 3개의 벤치마크 테스트를 수행하였다. 평균 제곱근 오차(Root Mean Squared Error, RMSE)를 산정하여 수치모형의 성능을 정량적으로 평가하였으며, 비소산함수를 적용함에 따라 스칼라의 수치확산이 감소하게 되었음을 확인하였다. 또한, 세 차례의 벤치마크 테스트 결과는 공통적으로 수치모형에 의해 계산된 결과값이 비소산함수를 고려함에 따라 해석해와 잘 일치함을 확인하였다.

• Tunnel and Underground Space
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• v.32 no.2
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• pp.144-159
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• 2022

The present study developed a sequential approach-based numerical simulator for modeling coupled thermal-hydrological-mechanical (THM) processes in the ground and investigated the computational performance of the coupling analysis algorithm. The present sequential approach linked the two different solvers: an open-source numerical code, OpenGeoSys for solving the thermal and hydrological processes in porous media and a commercial code, FLAC3D for solving the geomechanical response of the ground. A benchmark test of the developed simulator was carried out using a THM problem where an analytical solution is given. The benchmark problem involves the coupled behavior (variations in temperature, pore pressure, stress, and deformation with time) of a fully saturated porous medium which is subject to a point heat source. The results of the analytical solution and numerical simulation were compared and the validity of the numerical simulator was investigated.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1205-1208
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• 2003

본 논문에서는 분할된 스캔을 이용한 저전력 BIST 구조를 제안한다. 제안하는 BIST는 내부 스캔 패스를 회로의 구조적인 정보와 테스트 패턴 집합의 특성에 따라 4개의 스캔 패스로 분할하고 일부 스캔 패스에만 입력패턴이 인가되도록 설계하였다. 따라서 테스트 패턴 입력 시에 스캔 패스로의 쉬프트 동작 수를 줄임으로써 회로 내부의 전체 상태천이 수를 줄일 수 있다. 또한 4개로 분할되는 스캔패스의 길이를 고려하여 각 스캔 패스에 대해 1/4의 속도로 낮춰진 테스트 클럭을 인가함으로써 전체 회로의 전력 소모를 줄일 수 있도록 하였다. ISCAS89 벤치마크 회로에 대한 실험을 통하여 제안하는 BIST 구조가 기존 BIST 구조에 비해 최대 21%까지 전력소모를 줄일 수 있음을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.63-71
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• 2003

IDDQ testing is indispensable in improving Duality and reliability of CMOS VLSI circuits. But the major problem of IDDQ testing is slow testing speed due to time-consuming IDDQ current measurement. So one requirement is to reduce the number of target faults or to make the test sets compact in fault model. In this paper, we consider equivalent fault collapsing for transistor short faults, a fault model often used in IDDQ testing and propose an efficient algorithm for reducing the number of faults that need to be considered by equivalent fault collapsing. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.1
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• pp.1-7
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• 2014

This paper proposes an efficient test wrapper design that reduces overall test time in multi-core SoC. After initial local wrapper solution sets for all the cores are determined using well-known Combine algorithm, proposed algorithm selects a dominant core which consumes the longest test time in multi-core SoC. Then, the wrapper characteristics in the number of TAM wires and the test time for other cores are adjusted based on test time of the dominant core. For some specific cores, the number of TAM wires can be reduced by increasing its test time for design space exploration purposes. These modified wrapper characteristics are added to the previous wrapper solution set. By expanding previous local wrapper solution set to global wrapper solution set, overall test time for Multi-core SoC can be reduced by an efficient test scheduler. Effectiveness of the proposed wrapper is verified on ITC'02 benchmark circuits using $B^*$-tree based test scheduler. Our experimental results show that the test time is reduced by an average of 4.7% when compared to that of employing previous wrappers.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.6
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• pp.361-368
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• 2002

This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tacks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we are able to enhance the testability of circuits with very little overheads on design area and execution time.