• Title/Summary/Keyword: 범용부호

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Performance Analysis of Wireless Communication Networks for Smart Metering Implemented with Channel Coding Adopted Multi-Purpose Wireless Communication Chip (오류 정정 부호를 사용하는 범용 무선 통신 칩으로 구현된 스마트 미터링 무선 네트워크 시스템 성능 분석)

  • Wang, Hanho
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.64 no.4
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    • pp.321-326
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    • 2015
  • Smart metering is one of the most implementable internet-of-thing service. In order to implement the smart metering, a wireless communication network should be newly designed and evaluated so as to satisfy quality-of-service of smart metering. In this paper, we consider a wireless network for the smart metering implemented with multi-purpose wireless chips and channel coding-functioned micro controllers. Especially, channel coding is newly adopted to improve successful frame transmission probability. Based on the successful frame transmission probability, average transmission delay and delay violation probability are analyzed. Using the analytical results, service coverage expansion is evaluated. Through the delay analysis, service feasibility can be verified. According to our results, channel coding needs not to be utilized to improve the delay performance if the smart metering service coverage is several tens of meters. However, if more coverage is required, chanel coding adoption definitely reduces the delay time and improve the service feasibility.

Design and Implementation of RISC Processor for Speech Coding (음성부호 처리에 적합한 RISC 프로세서의 설계 및 구현)

  • Kim, Jin;Lee, Jun-Yong
    • Proceedings of the Korean Information Science Society Conference
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    • 2000.10c
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    • pp.18-20
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    • 2000
  • 디지털 음성통신을 위한 빠르고 쉬운 내장 프로세서(Embedded processor)가 요구되어짐에 따라 음성신호 압축 복원 알고리즘인 ADPCM과 LD-CELP의 구현에 가장 빈번히 사용되는 연산의 특성을 조사하였다. ARM6 processor core의 기본 구성요소들과 명령어집합을 기반으로 하여 음성부호화 알고리즘의 연산의 특성을 효율적으로 처리하기 위한 명령어와 구조를 추가한 범용 프로세서의 구조를 제안하고 VHDL로 기술하여 동작을 검증하였다. ARM6의 ALU logic에 leading zero count를 위한 회로를 추가하였고 opcode를 변경하였으며, LPC 계수 연산을 위해 제안된 MAC을 도입하여 효율적인 구현이 가능하도록 설계하였다.

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An Enhancement of the MPEG-2 Audio Encoder Using General DSPs (범용 DSP를 이용한 MPEG-2 오디오 부호화기의 성능 개선)

  • 오현오;김성윤;윤대희;차일환;이준용
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 1997.11a
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    • pp.63-67
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    • 1997
  • The ISO(International Standard Organization) has standardized MPEG-2 audio. The MPEG-2 audio compression algorithm is based upon subband analysis and exploits the human auditory characteristics to achieve a low bit rate with minimum perceptual loss of audio signal quality. This thesis presents an enhanced MPEG-2 audio encoder using multiple TMS320C30 general purpose DSP's. The developed system is made up of five slave boards and one master board. Each slave board performs susband analysis psychoacoustic parameter calculation for one channel, and the master board manages bit allocation, quantization, and bit-stream formatting for all channels. Parallel processing and pipelining techniques are used in hardware structure and fast algorithms are applied in each subroutine to implement a real-time process. The implemented system supports multichannel up to 5.1 and various bitrates.

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A Design of Profile Based Generational Garbage Collector in Java (자바에서 프로파일에 기초한 세대기반 가비지 콜렉터 설계)

  • 김일부호;오세만
    • Proceedings of the Korean Information Science Society Conference
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    • 1999.10a
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    • pp.388-390
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    • 1999
  • 자바는 자동 메로리 회수(garbage collection) 방식을 채택한 범용 프로그래밍 언어로 자바 가상머신(JVM)이 설치된 다양한 플랫폼에서 사용되어 지고 있다. 현재 자바에서 사용되는 가비지 콜렉터는 휴지(pause) 시간이 상당히 길어 짧은 응답시간을 요구하는 서버 및 실시간 응용 프로그램에는 적합하지 않은 표시-압축 기법을 사용한다. 이를 보완하기 위해 자바 HotSpotTM 성능 엔진에서 세대기반(generational) 복사 기법에 기반을 둔 혼성(hybrid) 가비지 콜렉터를 사용하고 있으나, 상당히 큰 오버헤드를 보이고 있어 다양한 응용 프로그램의 특성을 수용하기에는 개선의 여지가 많다. 본 논문에서는 세대기반 기법을 기반으로, 자바와 자바 가상머신이 가진 특성들과 실행시간 객체의 타입 및 스택 정보를 이용하는 가비지 콜렉터를 설계한다. 또한, 힙 프로파일 분석기를 구현하고, 이를 통해 응용 프로그램에 적합한 메모리 구조를 분석하고, 가비지 콜렉터에 적용할 수 있도록 한다.

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A Design of a Robust Vector Quantizer for Wavelet Transformed Images (웨이브렛벤환 영상 부호화용 범용 벡터양자화기의 설계)

  • Do, Jae-Su;Cho, Young-Suk
    • Convergence Security Journal
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    • v.6 no.4
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    • pp.83-90
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    • 2006
  • In this paper, we propose a new design method for a robust vector quantizer that is independent of the statistical characteristics of input images in the wavelet transformed image coding. The conventional vector quantizers have failed to get quality coding results because of the different statistical properties between the image to be quantized and the training sequence for a codebook of the vector quantizer. Therefore, in order to solve this problem, we used a pseudo image as a training sequence to generate a codebook of the vector quantizer; the pseudo image is created by adding correlation coefficient and edge components to uniformly distributed random numbers. We will clearly define the problem of the conventional vector quantizers, which use real images as a training sequence to generate a codebook used, by comparing the conventional methods with the proposed through computer simulation. Also, we will show the proposed vector quantizer yields better coding results.

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Design of High Performance Robust Vector Quantizer for Wavelet Transformed Image Coding (웨이브렛 변환 영상 부호화용 고성능 범용 벡터양자화기의 설계)

  • Jung, Tae-Yeon;Do, Je-Su
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.2
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    • pp.529-535
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    • 2000
  • In this paper, we propose a new method of designing the vector quantizer which is robustness to coding results and independent of statistical characteristics of an input image in wavelet transformed image coding processes. The most critical drawback of a conventional vector quantizer is the degradation of coding capability resulted from the discordance between quantizer objective image and statistical characteristics of training sequence which is for generating representing vector. In order to resolve the problem of conventional methods, we use independent random-variables and pseudo image to which image correlation and edge component were added, as a training sequence for generating representing vector. We have done a computer simulation in order to compare coding capability between a vector quantizer designed by the proposed method and one with the conventional method using real image as same as that is objective to coding of training sequence used in codebook generation. The results show the superiority of the proposed vector quantizer method at the aspect of coding capability compared to conventional one. They also clarify the problems of conventional methods.

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Comparison and analysis of compression algorithms to improve transmission efficiency of manufacturing data (제조 현장 데이터 전송효율 향상을 위한 압축 알고리즘 비교 및 분석)

  • Lee, Min Jeong;Oh, Sung Bhin;Kim, Jin Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.1
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    • pp.94-103
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    • 2022
  • As a large amount of data generated by sensors or devices at the manufacturing site is transmitted to the server or client, problems arise in network processing time delay and storage resource cost increase. To solve this problem, considering the manufacturing site, where real-time responsiveness and non-disruptive processes are essential, QRC (Quotient Remainder Compression) and BL_beta compression algorithms that enable real-time and lossless compression were applied to actual manufacturing site sensor data for the first time. As a result of the experiment, BL_beta had a higher compression rate than QRC. As a result of experimenting with the same data by slightly adjusting the data size of QRC, the compression rate of the QRC algorithm with the adjusted data size was 35.48% and 20.3% higher than the existing QRC and BL_beta compression algorithms.

Implementation of a G,723.1 Annex A Using a High Performance DSP (고성능 DSP를 이용한 G.723.1 Annex A 구현)

  • 최용수;강태익
    • The Journal of the Acoustical Society of Korea
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    • v.21 no.7
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    • pp.648-655
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    • 2002
  • This paper describes implementation of a multi-channel G.723.1 Annex A (G.723.1A) focused on code optimization using a high performance general purpose Digital Signal Processor (DSP), To implement a multi-channel G.723.1A functional complexities of the ITU-T G.723.1A fixed-point C-code are measures an analyzed. Then we sort and optimize C functions in complexity order. In parallel with optimization, we verify the bit-exactness of the optimized code using the ITU-T test vectors. Using only internal memory, the optimized code can perform full-duplex 17 channel processing. In addition, we further increase the number of available channels per DSP into 22 using fast codebook search algorithms, referred to as bit -compatible optimization.

Status of Profiles and Levels for JVT Video Coding Standard (JVT 동영상 국제표준 프로파일/레벨 동향)

  • 김해광;이상윤
    • Broadcasting and Media Magazine
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    • v.7 no.3
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    • pp.12-18
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    • 2002
  • JVT is an international video coding standard that is being developed jointly by VCEG of ITU and MPEG of ISO. The standardization efforts are targeted mainly for a very high compression ratio. JVT is a general video coding technology that may be used in various application fields. JVT began to work seriously on the profiles and levels issues since Geneva meeting, January 2002. Profiles are sub sets of technical tools from the entire tools and levels limit processing power and memory resources of a decoder As of now, three profiles of Baseline, Main and X (not defined name yet) and hierarchically structured levels are defined in JVT FCD. The profiling issue is very important for the JVT s initial objective of Baseline royalty free policy. Royalty free Baseline profiling is currently under practical hurdles and this issue may impact as one of critical factors on the success of JVT standard.

A Performance Evaluation of a RISC-Based Digital Signal Processor Architecture (RISC 기반 DSP 프로세서 아키텍쳐의 성능 평가)

  • Kang, Ji-Yang;Lee, Jong-Bok;Sung, Won-Yong
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.2
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    • pp.1-13
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    • 1999
  • As the complexity of DSP (Digital Signal Processing) applications increases, the need for new architectures supporting efficient high-level language compilers also grows. By combining several DSP processor specific features, such as single cycle MAC (Multiply-and-ACcumulate), direct memory access, automatic address generation, and hardware looping, with a RISC core having many general purpose registers and orthogonal instructions, a high-performance and compiler-friendly RISC-based DSP processors can be designed. In this study, we develop a code-converter that can exploit these DSP architectural features by post-processing compiler-generated assembly code, and evaluate the performance effects of each feature using seven DSP-kernel benchmarks and a QCELP vocoder program. Finally, we also compare the performances with several existing DSP processors, such as TMS320C3x, TMS320C54x, and TMS320C5x.

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