• Title/Summary/Keyword: 번지코드

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Vibration Mode Measurement Test of External Fuel Tank for Aircraft (항공기용 외부연료탱크 진동모드 측정시험)

  • Kim, Hyun-gi;Choi, Hyun Kyung;Kim, Sungchan;Park, Hyung Bae;An, Su Hong;Kim, Young Shin
    • Journal of Aerospace System Engineering
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    • v.16 no.4
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    • pp.88-94
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    • 2022
  • The vibration mode measurement test measures the natural vibration characteristics of the target specimen. The measured natural mode characteristics are compared with the numerical analysis result to verify the reliability of the numerical analysis. If necessary, it is used to supplement the numerical analysis model of the specimen used for the dynamic characteristic analysis. In this paper, the natural frequency and natural mode of the external fuel tank are respectively obtained through the vibration mode measurement test and the numerical analysis, using the finite element model. The results are compared to verify the reliability of the numerical analysis model of the external fuel tank to apply to the entire aircraft model. To measure the vibration mode of the test specimen, a bungee cord was used, to simulate the free boundary condition for the test specimen. And, 3-axis accelerometers were installed on the test specimen. The response characteristics of the test specimen were measured, by excitation with an impact hammer. As a result of the test, after performing the frequency response analysis on the response acceleration, the natural frequency of the test specimen and its vibration mode were confirmed. The reliability of the numerical analysis model was verified by comparing the frequency and vibration mode, obtained through the test and the numerical analysis.

Modal Test of the 2nd stage structure of KSLV-I (KSLV-I 2단부 구조체 모드 시험)

  • Seo, Sang-Hyeon;Jeong, Ho-Kyeong;Youn, Se-Hyun;Park, Soon-Hong;Jang, Young-Soon
    • Aerospace Engineering and Technology
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    • v.6 no.1
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    • pp.114-119
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    • 2007
  • This paper introduces modal test of the 2nd stage structure of KSLV-I which is composed to satellite, PLA(Payload Adapter), EB(Equipment Bay), KMS(Kick Motor Support) and KM(Kick Motor) without PLF(Payload Fairing). In this test, to simulate free-free boundary condition, test object was hung by 4 bungee cords and excited by using impact hammer. From this test, dynamic properties of the 2nd stage structure of KSLV-I can be obtained. Modal test data are analyzed by using TDAS(Test Data Analysis Software). As the result, modal parameters and mode shapes below 100Hz of the 2nd stage of KSLV-I were identified.

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Development of Postal Image Acquisition System for Sequence Sorting (우편물 이미지 획득 시스템 개발)

  • Song, Jae-Gwan;Lim, Kil-Tak;Kim, Doo-Sik;Nam, Yun-Seok
    • Proceedings of the Korea Information Processing Society Conference
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    • 2001.10b
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    • pp.1217-1220
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    • 2001
  • 우편물의 자동구분은 우편물을 OVIS(OCR-Video coding Integrated System)에 자동으로 공급하고 우편물의 수취인 주소영역을 카메라를 이용하여 획득한 다음 우편번호를 인식하여 바코드로 변환하여 인쇄하게 되고, 이 우편물은 LSM(Letter Sorting Machine)으로 보내져 BCR(Bar Code Reader)에 의해 인쇄된 바코드를 판독하여 행선지별로 구분하는 과정을 거친다. 주소의 번지 이하 부분은 배달원의 수작업에 의해 최종 배달지점 순서대로 정렬한 다음 배달하게 된다. 이 부분의 작업에 소요되는 시간은 배달원 일일 평균 4 시간에 달하며 원가절감 대상으로 지적되고 있다. 이 부분을 자동화하여 우편물 처리시간을 단축하고 생산성을 향상하는 방안이 대두되고 있으며, 이를 해결하기 위해 번지 부분까지 OCR을 이용, 인식하여 우편번호 및 순로 데이터 베이스에서 인식결과에 해당하는 코드를 추출하여 해당 구분 칸으로 우편물을 분류하는 방식을 택하면 집배원이 우편물을 배달하는 순로까지 자동으로 정렬할 수 있게 된다. 본 논문은 수취인 주소영역의 주소부분을 자동판독하기 위한 시스템을 개발한 내용을 다루고자 한다.

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The Presentation of Semi-Random Interleaver Algorithm for Turbo Code (터보코드에 적용을 위한 세미 랜덤 인터리버 알고리즘의 제안)

  • Hong, Sung-Won;Park, Jin-Soo
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.2
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    • pp.536-541
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    • 2000
  • Turbo code has excellent decoding performance but had limitations for real time communications because of the system complexity and time delay in decoding procedure. To overcome this problem, a new SRI(Semi-Random Interleaver) algorithm which realize the reduction of the interleaver size is proposed for reducing the time delay during the decoding prodedure. SRI compose the interleaver 0.5 size from the input data sequence. In writing the interleaver, data is recorded by row such as block interleaver. But, in reading, data is read by randomly and the text data is located by the just address simultaneously. Therefore, the processing time of with the preexisting method such as block, helical random interleaver.

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High-Speed Korean Address Searching System for Efficient Delivery Point Code Generation (효율적인 순로코드 발생을 위한 고속 한글 주소검색 시스템 개발)

  • Kim, Gyeong-Hwan;Lee, Seok-Goo;Shin, Mi-Young;Nam, Yun-Seok
    • The KIPS Transactions:PartD
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    • v.8D no.3
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    • pp.273-284
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    • 2001
  • A systematic approach for interpreting Korean addresses based on postal code is presented in this paper. The implementation is focused on producing the final delivery point code from various types of address recognized. There are two stages in the address interpretation : 1) agreement verification between the recognized postal code and upper part of the address and 2) analysis of lower part of the address. In the agreement verification procedure, the recognized postal code is used as the key to the address dictionary and each of the retrieved addresses is compared with the words in the recognized address. As the result, the boundary between the upper part and the lower part is located. The confusion matrix, which is introduced to correct possible mis-recognized characters, is applied to improve the performance of the process. In the procedure for interpreting the lower part address, a delivery code is assigned using the house number and/or the building name. Several rules for the interpretation have been developed based on the real addresses collected. Experiments have been performed to evaluate the proposed approach using addresses collected from Kwangju and Pusan areas.

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A New Semi-Random Imterleaver Algorithm for the Noise Removal in Image Communication (영상통신에서 잡음 제거를 위한 새로운 세미 랜덤 인터리버 알고리즘)

  • Hong, Sung-Won;Park, Jin-Soo
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.8
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    • pp.2473-2483
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    • 2000
  • In this paper, The turbo code is used to effectively remove noise which is generated on the image communication channel. Turbo code had excellent decoding performance. However, it had limitations for real time communication because of the system complexity and time delay in decoding procedure. To overcome this problem, this paper proposed a new SRI(Semi Random Interleaved algorithm, which decrease the time delay, when the image data, which reduced the interleaver size of turbo code encoder and decoder, transmitted. The SRI algorithm was composed of 0.5 interleaver size from input frame sequence. When the data inputs in interleaver, the data recorded by row such as block interleaver. But, When the data read in interleaver, the data was read by randomly and the next data located by the just address simultaneously. Therefore, the SRI reduced half-complexity when it was compared with pre-existing method such as block, helical, random interleaver. The image data could be the real time processing when the SRI applied to turbo code.

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Ground Vibration Tests of SmartUAV Airframe Structure (스마트무인기 기체구조물 지상진동시험)

  • Jeon, Byoung-Hee;Kang, Hui-Won;Lee, Jung-Jin;Lee, Young-Shin
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.38 no.5
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    • pp.482-489
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    • 2010
  • This paper describes the test procedure, instrumentation, verification methodology and the results of the ground vibration test(GVT) and force vibration test(FVT) of the SmartUAV aircraft to estimate experimentally dynamic characteristics of the aircraft. Bungee cords are used to emulate free-free boundary conditions of the test aircraft. The SmartUAV is excited by three shakers and one-hundred frequency response functions(FRF's) is measured. The FRF's are reduced and analyzed to identify the dynamics parameters of the SmartUAV. To extract modal parameters of the SmartUAV such as, natural frequencies and damping ratios, the poly-reference least square complex exponential method is used in the time domain. The mode shape coefficients are estimated with the least squares frequency domain method to identify the vibration modes. The FVT was performed by fixed sine frequency with three shakers on the x, y and z direction and vibration characteristics of structures and detail equipments are measured.

Free Vibration Characteristics of Rectangular Plates under Uniform Thermal Loading Part II. Experimental Modal Test (균일 열부가 하중을 받는 사각판의 자유 진동특성 연구 Part II. 고유진동 실험)

  • Jeon, Byoung-Hee;Kang, Hui-Won;Lee, Young-Shin
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.39 no.2
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    • pp.106-113
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    • 2011
  • This paper was conducted on experimental analysis in the free vibration analysis of rectangular plates under uniform thermal loading. Materials of three rectangular plates were aluminum, steel and stainless-steel respectively. The dimension of rectangular plates was 0.1 $\times$ 0.1 $\times$ 0.002 m. Infrared quartz lamps were used for thermal loading. The PCS(Power Control System) electric control system was applied for control and scanning vibrometer (Poly Tech) was used for acquisition of frequency response function. Applied temperature was increased from room temperature to $300^{\circ}C$ by $50^{\circ}C$. Boundary condition was free-free condition using bungee cord. Front face of rectangular plate was heated uniformly.

Design and FPGA Implementation of a High-Speed RSA Algorithm for Digital Signature (디지털 서명을 위한 고속 RSA 암호 시스템의 설계 및 FPGA 구현)

  • 강민섭;김동욱
    • The KIPS Transactions:PartC
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    • v.8C no.1
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    • pp.32-40
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    • 2001
  • In this paper, we propose a high-speed modular multiplication algorithm which revises conventional Montgomery's algorithm. A hardware architecture is also presented to implement 1024-bit RSA cryptosystem for digital signature based on the proposed algorithm. Each iteration in our approach requires only one addition operation for two n-bit integers, while that in Montgomery's requires two addition operations for three n-bit integers. The system which is modelled in VHDL(VHSIC Hardware Description Language) is simulated in functionally through the use of $Synopsys^{TM}$ tools on a Axil-320 workstation, where Altera 10K libraries are used for logic synthesis. For FPGA implementation, timing simulation is also performed through the use of Altera MAX + PLUS II. Experimental results show that the proposed RSA cryptosystem has distinctive features that not only computation speed is faster but also hardware area is drastically reduced compared to conventional approach.

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