• Journal of KIISE:Computer Systems and Theory
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• v.35 no.11
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• pp.527-539
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• 2008

This paper presents a performance estimation technique based on queuing analysis for on-chip bus matrix architectures of Multi-Processor System-on-Chips(MPSoCs). Previous works relying on time-consuming simulation are not able to explore the vast design space to cope with increasing time-to-market pressure. The proposed technique gives accurate estimation results while achieving faster estimation time than cycle -accurate simulation by order of magnitude. We consider the followings for the modeling of practical memory subsystem: (1) the service time with the general distribution instead of the exponential distribution and (2) multiple-outstanding transactions to achieve high performance. The experimental results show that the proposed analysis technique has the accuracy of 94% on average and much shorter runtime ($10^5$ times faster at least) compared to simulation for the various examples: the synthetic traces and real-time application, 4-channel DVR.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.69-78
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• 2010

To implement the high performance SoC, we propose the flying master bus architecture that a specially defined master named as the flying master directly accesses the selected slaves with no regard to the bus protocol. The proposed bus architecture was implemented through Verilog and mapped the design into Hynix 0.18um technology. As master and slave wrappers have around 150 logic gate counts, the area overhead is still small considering the typical area of modules in SoC designs. In TLM performance simulation about proposed architecture, 25~40% of transaction cycle and 43~60% of bus efficiency are increased and 43~77% of request cycle is decreased, compared with conventional bus architecture. Conclusively, we assume that the proposed flying master bus architecture is promising as the leading candidate of the bus architecture in the aspect of performance and efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2078-2082
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• 2010

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. Conventional arbitration method is considered bus priority primarily, actual bus utilization didn't considered. In this paper, we propose arbitration method using bus utilization operating block of each master, we verify the performance compared with the other arbitration methods through throughput performance. From the result of performance verification, we confirm that proposed arbitration method, matched bus utilization set by the user 40%, 20%, 20%, 20%.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04b
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• pp.502-504
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• 2004

지능형 교통 정보 시스템을 구축할 때 반드시 요구되는 것이 바로 위치 정보이다. 대부분 GPS (Global Positioning System)와 같은 장치를 이용하여 위치 정보를 얻게 된다. 그러나 GPS수신기와 같은 장치는 상대적으로 비용이 크기 때문에 차량마다 장착하여 지능형 교통 정보 시스템에 활용하기에는 부담이 된다. 따라서 본 논문에서는 기존의 무선랜으로 위치를 추적하는 방법을 버스 지능형 교통 정보 시스템에 적용한 시스템 구조를 제안한다. 버스는 노선의 자유도가 택시 같은 다른 교통편에 비해서 작으므로 무선랜으로 위치 추적하는 방법은 다른 위치 추적 방법에 비해 경제적으로 보다 적합하다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.7
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• pp.1282-1295
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• 1994

In this paper, a hierarchical cluster multiprocessor system based on a hierarchical bus system is proposed and its cache coherency protocol is designed and implemented. The hierarchical cluster architecture aims at elimination the system bottleneck of the existing single bus system by adding a hierarchy of buses as the number of clusters is increased. Therefore the system is easy to scale up to a large number of processors. The proposed cache protocol is designed to be adapted to the general N-level (N>2) hierarchical cluster architecture. The original pended protocol is extended to implement the cache protocol on the system bus and cache coherency operations for this protocol are explained.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1995.10a
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• pp.419-422
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• 1995

• Journal of Digital Convergence
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• v.19 no.11
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• pp.215-224
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• 2021

Business stakeholders have shown huge interests on the way how to increase business value by integrating real world businesses with a rising metaverse concept. To understanding the utility of metaverse regarding digital transformation, this study conducted a qualitative study based on a metaverse framework from 2006 Metaverse Roadmap and reference theories on business models. Specifically, a multiple comparative case approach was adopted to investigate three metaverse application cases from 2000 to 2020. From findings, it was revealed that different metaverse features were tried to leverage traditional simulation games, social communities, and virtual communication activities to build business models. Secondly, the use of metaverse features were likely to be helpful in getting competitive advantages. However, we are also aware that stakeholder credibility should be carefully managed to sustain businesses.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.8
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• pp.554-561
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• 2006

In recent years, as SoC design research is actively conducted, a large number of IPs are included in a system. Various bus protocols and bus architectures are designed to increase IP reusability. Among them, the AMBA AHB became a de facto standard although it is somewhat inadequate for a large scale SoC. We proposed SNP and SNA, high performance on-chip-bus protocol and architecture, respectively, to solve the problem of the conventional shared buses. However, it seems to be imperative that the new on-chip-bus system support AMBA-compatible IPs for a while since there are a lot of IPs with AMBA interface. In this paper, we propose an extended SNP specification and a corresponding SNA component to support ABMA-compatible IPs used in SNA - based system. We extend the phase of the SNP by 1 bit to add new 8 phases to support communication based on AMBA protocol without penalty of elongated cycle latency. The ARB-to -XSNP converter translates the protocol between AHB and SNP to attach AMBA -compatible IPs to SNA based system. We show that AMBA IPs can communicate through SNP without any degradation of performance using the extended SNP and AHB - to- XSNP converter.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.405-410
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• 2008

성능 / 에너지를 강조하는 현재의 멀티코어 추세에서 임베디드 시스템에 사용되는 대부분의 프로세서들은 단일 프로세서와 메모리를 버스 형태로 연결하여 구현하였다. 하지만 칩 내부의 프로세서 코어 수가 증가 하게 되면, 기존 버스 형태의 구조는 제한된 대역폭으로 인하여 확장성이 제약된다. 본 논문에서는 멀티코어 프로세서에서 사용 가능한 기존 연결 망 구조들을 분석하고, 기존 계층적 링 구조에서의 지연 시간 문제를 극복하여 성능을 개선할 수 있는 새로운 이중 광역 계층 링 구조를 제안한다.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.22 no.6
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• pp.208-222
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• 2023

With the recent revision of 「Act on Promotion of the Transportation Convenience of Mobility Disadvantaged Persons」 and the Enforcement Regulations of the Act, bus business operators must introduce low-floor buses when scrapping buses. On the other hand, in the case of routes where low-floor buses cannot be operated, bus business operators can be exempted from introducing low-floor buses with the approval of their transportation administrative agency according to Article 4-2 of 「Enforcement Regulation of the Act on Promotion of the Transportation Convenience of Mobility Disadvantaged Persons」. According to the data from the Korea Bus Transportation Associations Federation, approximately 5.9% of all city bus routes were surveyed as the exceptions to introducing low-floor buses. Nevertheless the proportion is expected to increase because some regions with difficulties introducing low-floor buses are not included when calculating the proportion. By confirming the process of approving exceptions for introducing low-floor buses through local governments, there was no specific examination method or standard for approval of exceptions. Hence, there is the problem that some routes are approved as exceptions to introducing low-floor buses, even though low-floor buses can be operated on those routes. Therefore, this study aims to develop a manual that can objectively diagnose the overall operation environment of low-floor buses, such as road geometry and road facilities. Future research plans to apply it to more cases and improve it for more precise application in various contexts.