• Journal of radiological science and technology
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• v.39 no.1
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• pp.35-42
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• 2016

Room-temperature operating CdZnTe(CZT) material is an innovative radiation detector which could reduce the patient dose to one-tenth level of conventional CT (Computed Tomography) and mammography system. The pixel and pixel pitch in the imaging device determine the conversion efficiency of incident X-or gamma-ray and the cross-talk of signal, that is, image quality of detector system. The weighting potential is the virtual potential determined by the position and geometry of electrode. The weighting potential obtained by computer-based simulation in solving Poisson equation with proper boundaries condition. The pixel was optimized by considering the CIE (charge induced efficiency) and the signal cross-talk in CT detector system. The pixel pitch was 1-mm and the detector thickness was 2-mm in the simulation. The optimized pixel size and inter-pixel distance for maximizing the CIE and minimizing the signal cross-talk is about $750{\mu}m$ and $125{\mu}m$, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.6
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• pp.604-609
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• 2019

In this study, we fabricated a capacitive humidity sensor with interdigitated (IDT) electrodes using a thermosetting polyimide as a humidifying material. First, the number of electrodes, thickness, and spacing of the polyimide film were optimized, and a mask was designed and fabricated. The sensor was fabricated on a silicon substrate using semiconductor processing equipment. The area of the sensor was $1.56{\times}1.66mm^2$, and the width of the electrode and the gap between the electrodes were each $3{\mu}m$. The number of electrodes was 166, and the length of an electrode was 1.294 mm for the sensitivity of the sensor. The sensor was then packaged on a PCB for measurement. The sensor was inserted into a chamber environment with a temperature of $25^{\circ}C$ and connected to an LCR meter to measure the change in capacitance at relative humidity (RH) of 20% to 90%, 1 V, and 20 kHz. The results showed a sensitivity of 26fF/%RH, linearity of < ${\pm}2%RH$, and hysteresis of < ${\pm}2.5%RH$.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.1-10
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• 2018

Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.170.1-170.1
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• 2015

안티모니 (Sb)를 기반으로 한 제2형 초격자 (Type II superlattice, T2SL)구조 적외선 검출기 연구는 2000년대 들어 Sb 계열의 화합물 반도체 성장 기술이 발전함에 따라 HgCdTe (MCT), InSb, 양자우물 적외선 검출기 (QWIP)를 대체할 수 있는 고성능의 양자형 적외선 검출 소재로 부상하였으며, 현재 전 세계적으로 활발한 연구가 진행되고 있다. 특히, 기존의 양자형 적외선 검출소자에 비해 전자의 유효질량이 상대적으로 커서 밴드 간의 투과전류가 줄어들 뿐만 아니라, 전자와 정공이 서로 다른 물질 영역에 분포하여 Auger 재결합률을 효과적으로 줄일 수 있어 상온 동작이 가능한 소재로 주목을 받고 있다. 또한, T2SL 구조는 초격자를 구성하는 물질의 두께나 조성 변화를 통한 밴드갭 변조가 용이하여 단파장에서 장파장 적외선에 이르는 광범위한 파장 대역에서 동작이 가능할 뿐만 아니라 구조적 변화를 통해 이중 대역을 동시에 검출 할 수 있는 차세대 적외선 열영상 소자로 알려져 있다. 본 연구에서는 분자선 에피택시(MBE)법을 이용하여 300 주기의 InAs/GaSb (10/10 ML) 제2형 초격자 구조를 성장하여 적외선 검출소자를 제작하였다. 제2형 초격자 구조를 구성하는 물질계에 p-type dopant인 Be을 이용하여 각각 도핑 농도가 다른 시료를 성장하였다. 이때 p-type 도핑 농도는 각각 $1/5/10{\times}10^{15}cm^{-3}$로 변화를 주었다. 성장된 시료의 구조적 특성 분석을 위해 고분해능 X선 회절 (High resolution X-ray diffraction, HRXRD)법을 이용하였으며, 초격자 한 주기의 두께가 6.2~6.4 nm 로 설계된 구조와 동일하게 성장됨을 확인 하였으며, 1차 위성피크의 반치폭은 30~80 arcsec로 우수한 결정성을 가짐을 확인하였다. 적외선 검출을 위한 $410{\times}410{\mu}m^2$ 크기의 단위 소자 공정을 진행하였으며 이때 적외선의 전면 입사를 위해 소자 위에 $300{\mu}m$의 윈도우 창을 제작하였다. 단위 소자의 측벽에는 표면 누설 전류가 흐르는데 이를 방지하기 위해서 표면보호막을 증착하였다. 적외선 검출 소자의 전기적 특성 평가를 위해 각각의 시료의 암전류 (dark current)와 파장별 반응 (spectral response)을 온도별로 측정하여 비교 및 분석하였다.

• Journal of the Korean Vacuum Society
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• v.18 no.6
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• pp.411-417
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• 2009

The constant volume flow meter system (the chamber volume in the 22 L class) was developed to estimate the pumping speed of the dry pump used for the industry of the next generation semiconductor and display. In order to insure the validity of the system, The base pressure and the leak rate in the enclosed system were checked, which were the $6{\times}10^{-8}\;mbar$ and $1.5{\times}10^{-6}\;mbar-L/s$, respectively. Furthermore, it is also confirmed that the value of throughput limit in this system was as much as 1 order of magnitude lower than that in a previously developed system in the 875 L class. By using this developed system, the pumping speed of the new small dry pump was measured. It is believed that the new developed system can be alternating the expensive constant pressure flow meter system in the range of $1{\times}10^{-2}\;mbar-L/s{\sim}1{\times}10^{-3}\;mbar-L/s$.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.3
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• pp.20-40
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• 2003

Since unloaded Q-value of a high-temperature superconductor(HTS) filter is very high, a bandpass filter(BPF) and a lowpass filter(LPF) with an increase of pole numbers can be fabricated without an increase of an insertion loss(IL) ; recently a 70-pole BPF is developed in USA. They have an abrupt skirt property and an excellent attenuation level for out-of band. Moreover, they can be miniaturized when lumped element resonators or the slow-wave characteristic are used. Technology of fabricating a HTS epitaxial film as well as a film of a 4 inch area also makes the planar type filter with a various structure and an enhanced power handling capability possible. Recently, the HTS filter subsystems composed of a planar-type HTS filters, a GaAs-based LNA and a mini-cryocooler are developed. The extended receiver front- end subsystems for mobile radio communications decrease the noise-figure level of the communication system and the frequency interference interacted adjacent bands, and increase the efficiency of frequency and the capacity of communication system. In this paper, theory for developing the HTS filter, its kinds, its design rules, its characteristics are reviewed. The feature of the research and market trends related to the HTS filter systems for the receiver front-end subsystem of mobile base station are surveyed.

• Journal of the Korea Society of Computer and Information
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• v.17 no.7
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• pp.1-11
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• 2012

As process technology scales down, the number of cores integrated into a processor increases dramatically, leading to significant performance improvement. Especially, the GPU(Graphics Processing Unit) containing many cores can provide high computational performance by maximizing the parallelism. In the GPU architecture, the access latency to the main memory becomes one of the major reasons restricting the performance improvement. In this work, we analyze the performance improvement of the 3D GPU architecture compared to the 2D GPU architecture quantitatively and investigate the potential problems of the 3D GPU architecture. In general, memory instructions account for 30% of total instructions, and global/local memory instructions constitutes 60% of total memory instructions. Therefore, the performance of the 3D GPU is expected to be improved significantly compared to the 2D GPU by reducing the delay of memory instructions. However, according to our experimental results, the 3D architecture improves the GPU performance only by 2% compared to the 2D architecture due to the memory bottleneck, since the performance reduction due to memory bottleneck in the 3D GPU architecture increases by 245% compared to the 2D architecture. This paper provides the guideline for suitable memory design by analyzing the efficiency of the memory architecture in 3D GPU architecture.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1777-1783
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• 2014

In this paper, we designed and fabricated a high-speed semiconductor sensor for use in power control devices and analyzed the characteristics with pulsed radiation tests. At first, radiation sensitive circular Si PIN diodes with various diameters(0.1 mm ~5.0 mm) were designed and fabricated using Si epitaxial wafer, which has a $42{\mu}m$ thick intrinsic layer. The reverse leakage current of the diode with a radius of 2 mm at a reverse bias of 30 V was about 20.4 nA. To investigate the characteristic responses of the developed diodes, the pulsed gamma-radiation tests were performed with the intensity of 4.88E8 rad(Si)/sec. From the test results showing that the output currents and the rising speeds have a linear relationship with the area of the sensors, we decided that the optimal condition took place at a 2 mm diameter. Next, for the selected 2 mm diodes, dose rate tests with a range of 2.47E8 rad(Si)/sec to 6.21E8 rad(Si)/sec were performed. From the results, which showed linear characteristics with the radiation intensity, a large amount of photocurrent over 60mA, and a high speed response under 350ns without saturation, we can conclude that the our developed PIN diode can be a good candidate for the sensor of power control devices.

• Korean Journal of Materials Research
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• v.9 no.3
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• pp.274-281
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• 1999

Usually sputtering and electroless plating methods were used for manufacturing metal-alloy thin film magnetic memory devices. Since electroless plating method has many merits in mass production and product variety com­pared to sputtering method, many researches about electroless plating have been performed in the United State of America and Japan. However, electroless plating method has not been studied frequently in Korea. In these respects the purpose of this research is manufacturing Co-Mn-P alloy thin film on the corning glass 2948 by electroless plating method using sodium hypophosphite as a reductant, and analyzing deposition rate, alloy composition, microstructure, and magnetic characteristics at various pH's and temperatures. For Co-P alloy thin film, the reductive deposition reaction 0$\alpha$urred only in basic condition, not in acidic condition. The deposition rate increased as the pH and temperature increased, and the optimum condition was found at the pH of 10 and the temperature of $80^{\circ}C$. Also magnetic charac­teristics was found to be most excellent at the pH of 9 and the temperature of $70^{\circ}C$, resulting in the coercive force of 8700e and the squareness of 0.78. At this condition, the contents of P was 2.54% and the thickness of the film was $0.216\mu\textrm{m}$. For crystal orientation, we could not observe fcc for $\beta$-Co. On the other hand,(1010), (0002), (1011) orientation of hcp for a-Co was observed. We could confirm the formation of longitudinal magnetization from dominant (1010) and (1011) orientation of Co-P alloy. For Co-Mn-P alloy deposition, coercive force was about 1000e more than that of Co P alloy, but squareness had no difference. For crystal orientation, (l01O) and (lOll) orientation of $\alpha$-Co was dominant as same as that of Co- P alloy. Likewise we could confirm the formation of longitudinal magnetization.

• Journal of Korean Society of Environmental Engineers
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• v.29 no.6
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• pp.715-721
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• 2007

Residual calcium concentration is high, in general, at the effluent of the fluoride removal process in the electronics industry manufacturing semiconductor and LCD. To increase the stability of the membrane process incorporated for reuse of wastewater, the residual calcium is required to be pre-removed. Hyperkinetic Vortex Crystallization(HVC) process was installed in the electronics industry manufecturing semi conductor as a pilot scale for accelerating calcification of calcium ion. Compared to the conventional soda ash method, the 31% higher calcium removal efficiency was achieved when HVC was applied at the same sodium carbonate dosage. In order to maintain the economic calcium removal target of 70% preset by manufacturer, the dosing concentration of the soda ash was 530 mg/L based on influent flowrate. The seed concentration in the reactor was one of the critical factors and should be maintained in the range of $800\sim1,200mg$ SS/L to maximize the calcium removal efficiency. The calcite production rate was 0.30 g SS/g $Na_2CO_3$ in the average. The economic HVC passing time of the mixture was in the range of $2\sim5$ times. Relatively, stable calcium concentration was maintained in the range of $30\sim72$ mg/L(average 49 mg/L) although the calcium concentration in the feed was severely fluctuated with $74\sim359$ mg/L(average 173 mg/L). The HVC process was characterized as environment-friendly technology reducing chemical dosage and chemical sludge production and minimizing maintenance cost.