• Title/Summary/Keyword: 반도체설계기술

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FPGA Implementation and Verification of A Pipelined 32-bit ARM Processor (파이프라인 방식의 32 비트 ARM 프로세서에 대한 FPGA 구현 및 검증)

  • Lee, Jongbok
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.22 no.5
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    • pp.105-110
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    • 2022
  • Domestically, we are capable of designing high-end memory semiconductors, but not in processors, resulting in unbalance. Using Vivado as a development enivronment and implementing the processor on a Xilinx FPGA reduces time and cost dramatically. In this paper, the popular language VHDL which is widely used in Europe, universities, and research centers around the world for the digital system design is used for designing a pipelined 32-bit ARM processor, implemented on FPGA and verified by Integrated Logic Analyzer. As a result, the ARM processor implemented on FPGA could execute ARM instructions successfully.

발명계 소식

  • (사)한국여성발명협회
    • The Inventors News
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    • no.17
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    • pp.3-4
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    • 2003
  • 기능성 보도 블록, 특허 출원 증가 - 한$\cdot$$\cdot$일, 3국간 특허협력 본격 추진 - SK텔레콤 스피드 010 상표등록 추진 - LG전자, 미국서 세탁기 특허침해 피소 - 올해 가장 쿨한 발명품 - `반도체배치설계 공모전` 시상식 개최 - 한국 기술경쟁력 세계6위 - 특허청 분쟁조정위원회 유명무실 - 북한 특허등록 대행변리사 등장

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MMIC 기술 동향

  • Kim, Dong-Gu;Park, Hyeong-Mu
    • ETRI Journal
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    • v.9 no.3
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    • pp.127-138
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    • 1987
  • 본고에서는 MMIC (Monolithic Microwave Integrated Circuit)의 연구동향을 미국을 중심으로 소개한다. MMIC의 역사, 공정, 소자, 설계, packaging, 측정에 대하여 조사함으로써 차세대 화합물반도체 MMIC개발의 앞으로의 방향을 모색하고자 한다. 본고는 미국 Microwave & RF 논문지 1987년 3월호에 게재된 R. S. Pegally와 D. Maki의 논문내용을 중심으로 편역한 것이다.

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V-NAND Flash Memory 제조를 위한 PECVD 박막 두께 가상 계측 알고리즘

  • Jang, Dong-Beom;Yu, Hyeon-Seong;Hong, Sang-Jin
    • Proceedings of the Korean Vacuum Society Conference
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    • 2014.02a
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    • pp.236.2-236.2
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    • 2014
  • 세계 반도체 시장은 컴퓨터 기능이 더해진 모바일 기기의 수요가 증가함에 따라 메모리반도체의 시장규모가 최근 빠른 속도로 증가했다. 특히 모바일 기기에서 저장장치 역할을 하는 비휘발성 반도체인 NAND Flash Memory는 스마트폰 및 태블릿PC 등 휴대용 기기의 수요 증가, SSD (Solid State Drive)를 탑재한 PC의 수요 확대, 서버용 SSD시장의 활성화 등으로 연평균 18.9%의 성장을 보이고 있다. 이러한 경제적인 배경 속에서 NAND Flash 미세공정 기술의 마지막 단계로 여겨지는 1Xnm 공정이 개발되었다. 그러나 1Xnm Flash Memory의 생산은 새로운 제조설비 구축과 차세대 공정 기술의 적용으로 제조비용이 상승하는 단점이 있다. 이에 따라 제조공정기술을 미세화하지 않고 기존의 수평적 셀구조에서 수직적 셀구조로 설계 구조를 다양화하는 기술이 대두되고 있는데 이 중 Flash Memory의 대용량화와 수명 향상을 동시에 추구할 수 있는 3D NAND 기술이 주목을 받게 되면서 공정기술의 변화도 함께 대두되고 있다. 3D NAND 기술은 기존라인에서 전환하는데 드는 비용이 크지 않으며, 노광장비의 중요도가 축소되는 반면, 증착(Chemical Vapor Deposition) 및 식각공정(Etching)의 기술적 난이도와 스텝수가 증가한다. 이 중 V-NAND 3D 기술에서 사용하는 박막증착 공정의 경우 산화막과 질화막을 번갈아 증착하여 30layer 이상을 하나의 챔버 내에서 연속으로 증착한다. 다층막 증착 공정이 비정상적으로 진행되었을 경우, V-NAND Flash Memory를 제조하기 위한 후속공정에 영향을 미쳐 웨이퍼를 폐기해야 하는 손실을 초래할 수 있다. 본 연구에서는 V-NAND 다층막 증착공정 중에 다층막의 두께를 가상 계측하는 알고리즘을 개발하고자 하였다. 증착공정이 진행될수록 박막의 두께는 증가하여 커패시터 관점에서 변화가 생겨 RF 신호의 진폭과 위상의 변화가 생긴다는 점을 착안하여 증착 공정 중 PECVD 장비 RF matcher와 heater에서 RF 신호의 진폭과 위상을 실시간으로 측정하여 데이터를 수집하고, 박막의 두께와의 상관성을 분석하였다. 이 연구 결과를 토대로 V-NAND Flash memory 제조 품질향상 및 웨이퍼 손실 최소화를 실현하여 제조 시스템을 효율적으로 운영할 수 있는 효과를 기대할 수 있다.

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Measurement of Condensation and Boiling Heat Transfer Coefficients of Non-flammable Mixed Refrigerant for Design of Cryogenic Cooling System for Semiconductor Etching Process (반도체 식각 공정용 초저온 냉각 시스템 설계를 위한 비가연성 혼합냉매 응축 및 비등 열전달 계수 측정)

  • Cheonkyu Lee;Jung-Gil Lee
    • Journal of the Semiconductor & Display Technology
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    • v.22 no.3
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    • pp.119-124
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    • 2023
  • In this study, experimental approach of the measurement of condensation and evaporation heat transfer coefficients is discussed for mixed refrigerants using in the ultra low-temperature cooling system for semiconductor etching process. An experimental apparatus was described performing the condensation and evaporation heat transfer measurements for mixed refrigerants. The mixed refrigerant used in this study was composed of the optimal mixture determined in previous research, with a composition of Ar:R14:R23:R218 = 0.15:0.4:0.15:0.3. The experiments were conducted over a temperature range from -82℃ to 15℃ and at pressures ranging from 18.5 bar to 5 bar. The convection heat transfer coefficients of the mixed refrigerant were measured at flow rates corresponding to actual operating conditions. The condensation heat transfer coefficient ranged from approximately 0.7 to 0.9 kW/m2K, while the evaporation heat transfer coefficient ranged from 1.0 to 1.7 kW/m2K. The detailed discussion of the experimental methods, procedures, and results were described in this paper.

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A Study on Design of Intelligent Wet Station for Semiconductor (지능형 반도체 세정장비 설계에 관한 연구)

  • Kim Jong Won;Hong Kwagn Jin;Cho Hyun Chan;Kim Kwang Sun;Kim Doo Yong;Cho Jung Keun
    • Journal of the Semiconductor & Display Technology
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    • v.4 no.3 s.12
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    • pp.29-33
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    • 2005
  • As the integrated devices become more and more sophistcated, the diameter of wafers increased up to 300 mm and strict level of cleaning is necessary to remove the particulates on the surface of wafer. Therefore we need a new type of wet-station which can reduce DI water and chemical in the cleaning process. Moreover, it is important to control the temperature and the concentration of chemical in the wet-station. In the conventional chemical supply system, it is difficult not only to fit the mixing rate of chemicals in cleaning process, but also to fit the quantity and temperature. Thus, we propose a new chemicals supply system, which overcomes above problems by the analysis of fluid and thermal transfer on chemical supply system.

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Design Alterations of a Grinder of Semiconductor Wafer for the Improved Stability (반도체 Wafer용 Grinder의 안정화 설계)

  • Kil, Sa Geun;Ro, Seung Hoon;Shin, Yun Ho;Kim, Young Jo;Kim, Geon Hyeong
    • Journal of the Semiconductor & Display Technology
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    • v.16 no.1
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    • pp.91-96
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    • 2017
  • One of the most critical aspects of the modern semiconductor industry is the quality of wafer surface, the roughness of which is mostly caused by the ingot slicing. And the grinding is supposed to be the main process to reduce the surface roughness. The vibrations of the disc surface grinder are the major problem to effectively achieve the required surface quality. In this study, the structure of a disc surface grinder was analyzed through the experiment and the computer simulation to investigate the dynamic characteristics of the machine, and further to alter the design for the improved stability. The result of the study shows that simple design alterations without alternating main body can effectively suppress the vibrations of the machine.

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Structural Design of an Ingot Grower of the Semiconductor Wafer for the Stability Improvement (반도체 Wafer용 Ingot Grower 안정화를 위한 구조설계)

  • Yi, Il Hwan;Ro, Seung Hoon;Nam, Kyu Dong;Kang, Shin Won;Kim, Young Jo;Kim, Geon Hyeong
    • Journal of the Semiconductor & Display Technology
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    • v.16 no.1
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    • pp.34-39
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    • 2017
  • Semiconductor is one of the most internationally competitive areas among domestic industries, the major concern of which is the stability of the wafer manufacturing processes. The first process for the manufacturing of the semiconductor wafers is the ingot growing. The vibrations are supposed to be the most important factors for the ingot quality. In order to maintain the ingot quality, the growers have the automatic shut-down equipments which are activated by vibrations, and are sensitive enough to react to the earthquakes generated in Japan. In this study, the structure of an ingot grower was analyzed through experiments and computer simulations, and further the effects of design alterations to suppress the vibrations have been investigated. The final result shows that the vibrations can be reduced substantially to improve the stability of the structure.

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Design Alterations of a Semiconductor Wafer Edge Grinder for the Improved Stability (반도체 Wafer용 Edge Grinding Machine의 구조 안정화를 위한 설계 개선)

  • Park, Yu Ra;Ro, Seung Hoon;Kim, Young Jo;Kil, Sa Geun;Kim, Geon Hyeong;Shin, Yun Ho
    • Journal of the Semiconductor & Display Technology
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    • v.15 no.1
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    • pp.56-64
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    • 2016
  • It is generally accepted that the surface quality of wafer edge is mostly damaged by the vibrations of the edge grinding machine. The surface quality of wafer edge is supposed to be the most dominant factor of the cracks, scratches, burrs and chips on the edge surfaces, which are the main defects of the wafers. In this study, the structure of a wafer edge grinder has been investigated through the frequency response experiment and the computer simulation to find ways to suppress the vibrations from the structure. The main reasons of the structural vibrations were analyzed. And further the design alterations were deduced from the results of the experiment and the simulation, and applied to the machine to check the effects of those alterations and to eventually improve the structural stability. The result shows that the machine can have much improved stability with relatively simple design changes.

Trajectory Tracking Controller for Semiconductor Equipment Motors based on PI Observer (PI 관측기 기반 반도체 장비 모터의 궤적 추종 제어기 설계)

  • Yun Seong Cho;Hyeon Jun Choi;Sang Min Jeon;Ji Hoon Shin;Jae Young Lee;Bum Joo Lee;Young Ik Son
    • Journal of the Semiconductor & Display Technology
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    • v.22 no.2
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    • pp.96-103
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    • 2023
  • This paper presents a robust position tracking controller for a motor used in semiconductor equipment, utilizing the motor angle measurement. Precise position control is challenging due to the presence of uncertainties in various motor applications. The proposed controller consists of a PD (Proportional-Derivative) controller and a PIO (Proportional-Integral Observer) to estimate the system's state and equivalent disturbance compensating for the uncertainties. Since the stability alternates as the observer gain increases, we have investigated it through the closedloop root locus under the system parameters change. The analysis has showed that the inertia of the motor is the main parameter that affects it, and by adjusting the control gain appropriately, the system can be rendered to be stable even when the inertia of the motor changes. The effectiveness of the proposed control algorithm is validated through computer simulations, followed by a comparison of its performance with the results of a previous study.

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