• Korean Journal of Materials Research
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• v.2 no.5
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• pp.353-359
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• 1992

Thermal oxidation and plasma enhanced chemical vapor deposition of tantalum oxide thin films on p-type (100) Si substrates were studied to examine the dielectric nature of T$a_2O_5$ as a Al/T$a_2O_5$/p-Si capacitor. Microstructure and dielectric properties of the capacitors were investigated by XRD, AES, high frequency C-V analyzer, I-V meter and TEM. XRD analysis showed that the structure of T$a_2O_5$ films were amorphous, but the films were crystallized to hexagonal $\delta$-T$a_2O_5$ by 65$0^{\circ}C$ thermal oxidation treatment. It was found that the stoichiometry of the films was more or less close to 2 : 5. Leakage current density and relative dielectric constant of thermal oxidation T$a_2O_5$ film at 60$0^{\circ}C$ was 5.0${ imes}10^{-6}$/A/c$m^2 and 31.5, respectively. In the case of PECVD T$a_2O_5$film deposited at 0.47W/c$m^2 they were 2.5${ imes}10^{-5}$/A/$ extrm{cm}^2$ and 24.0, respectively. The morphology of the films and interfaces were investigated by TEM.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.1-10
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• 2018

Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.