• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.5
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• pp.723-730
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• 2016

Solar cells in a PV module are connected in series and parallel to produce a higher voltage and current. The PV module has performance characteristics depending on solar radiation and temperature. In addition, the PV system causes power loss by special situations, including the shadows of the surrounding environment, such as nearby buildings and trees. In other words, an increase in power loss and a decrease in life cycle can occur because of the partial shadow and hot-spot effect. Therefore, this paper proposes the optimal configuration algorithm of a bypass diode to improve the output of a PV module and one of a PV array to minimize the loss of the PV array. In addition, this paper presents a model of a PV module and PV array based on the PSIM S/W. The simulation results confirmed that the proposed optimal configuration algorithms are useful tools for improving the performance of PV system.

• Journal of Chest Surgery
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• v.30 no.5
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• pp.471-478
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• 1997

Introduction: The use of rabbits as a cardiopulmonary bypass(CPB) animal model is extremely dif%cult mainly due to technical problems. On the other hand, deep hypothermic circulatory arrest(CA) is used to facilitate surgical repair in a variety of cardiac diseases. Although steroids are generally known to be effective in the treatment of cerebral edema, the protective effects of steroids on the brain during CA are not conclusively established. Objectives of this study are twofold: the establishment of CPB technique in rabbits and the evaluation of preventive effect of steroid on the development of brain edema during CA. Material '||'&'||' Methods: Fifteen New Zealan white rabbits(average body weight 3.5kg) were divided into three experimental groups; control CA group(n=5), CA with Trendelenberg position group(n=5), and CA with Trendelenberg position + steroid(methylprednisolone 30 mglkg) administration group(n=5). After anesthetic induction and tracheostomy, a median sternotomy was performed. An aortic cannula(3.3mm) and a venous ncannula(14 Fr) were inserted, respectively in the ascending aorta and the right atrium. The CPB circuit consisted of a roller pump and a bubble oxygenator. Priming volume of the circuit was approximately 450m1 with 120" 150ml of blood. CPB was initiated at a flow rate of 80~85ml/kg/min, Ten min after the start of CPB, CA was established with duration of 40min at $20^{\circ}C$ of rectal temperature. After CA, CPB was restarted with 20min period of rewarming. Ten min after weaning, the animal was sacrif;cod. One-to-2g portions of the following tissues were rapidly d:ssected and water contents were examined and compared among gr ups: brain, cervical spinal cord, kidney, duodenum, lung, heart, liver, spleen, pancreas. stomach. Statistical significances were analyzed by Kruskal-Wallis nonparametric test. Results: CPB with CA was successfully performed in all cases. Flow rate of 60-100 mlfkgfmin was able to be maintained throughout CPB. During CPB, no significant metabolic acidosis was detected and aortic pressure ranged between 35-55 mmHg. After weaning from CPB, all hearts resumed normal beating spontaneously. There were no statistically significant differences in the water contents of tissues including brain among the three experimental groups. Conclusion: These results indicate (1) CPB can be reliably administered in rabbits if proper technique is used, (2) the effect of steroid on the protection of brain edema related to Trendelenburg position during CA is not established within the scope of this experiment.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.81-92
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• 2013

The satellite includes many release mechanisms such as solar array deployment, antenna deployment, cover to protect contamination in scientific equipment, pyro value of the propulsion subsytem, and bypass device in Li-Ion cell module. A drive the initiators is a critical to the successful mission because the initiators of release mechanism driving by the pyrotechnic circuit is operated in single short. The pyrotechnic circuit has to provide switching network for safety. A typical switching network has defect consisting of high current rating fire switch to handle switching transient current during fire the initiator. The pyrotechnic circuit is required some form of power conditioning to reduce the peak power demanded from the bus if the initiators are to be fired from the main bus. This paper design a pyrotechnic circuit synchronized to the fire-command to activate the fire switch to overcome use high current rating fire switch to handle switching transient current during fire the initiator. The pyrotechnic circuit provides a current limited widow pulse for fire current synchronized to the fire-command to insure that fire switch will only carry the current but never switch it. The current limited widow pulse for fire current can be possible to use low current rating and light mass switch in switching network. The current limit function in the pyrotechnic circuit reduces supply voltage to initiator and provides the effect of power conditioning function to reduce peak bus power. The pyrotechnic circuit to apply satellite development on geostationary orbit is verified the function by test in development model.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.2
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• pp.176-188
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• 1999

태스크의 마감 시간을 고려하지 않는 시분할 스케쥴링 방식으로 인하여 범용 운영 체제는 실시간 시스템을 개발하는데 적합하지 않다고 알려져 있다. 그러나 범용 운영 체제상에서 실시간 스케쥴링을 지원할수 있다면 개발된 시스템은 높은 이식성, 훌륭한 개발환경의 활용, 그리고 개발된 시스템을 위한 낮은 유지 보수 및 보수 비용 등 범용 운영 체제 고유의 중요한 장점들을 얻을 수있다. 본 논문에서는 범용 운영 체제인 Unix 상에 태스크의 마감 시간을 고려함으로써 실시간 고려함으로써 실시간 스케쥴링을 지원할 수 있는 새로운 기법을 제안한다. 제안된 기법은 특수한 태스크인 스케쥴링 데몬이 수행되는 실시간 태스크들 중 마감 시간이 가장 임박한 하나만을 수행 준비 상태로만들고, 그 외의 다른 시릿간 태스크들은 모두 수면 상태에 있도록 만드는 방식을 사용한다. 따라서 Unix 스케쥴러는 항상 유일한 태스크만을 스케쥴링의 대상으로하므로 시분할 방식의 Unix 스케쥴링 전략을 바이패스할 수 있으며, 이 결과 스케쥴링 데몬의 전략에 의하여 모든 실시간 태스크들을 스케쥴링 할 수 있다. 본 연구에서는 제안된 실시간 스케쥴링 데몬 기법을 Unix상에서 구현하였으며, C 언어 라이브러리 함수 형태의 API를 제공함으로써 실시간 시스템 개발자가 쉽게 시스템을 개발할수 있는 플랫폼을 구축하였다. 또한 실험을 통하여 이용한 성능 분석을 통하여 기존의 기법들과 비교한 제안된 기법의 우수성을 보였다.

• Transactions of the Korean Society of Mechanical Engineers
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• v.10 no.1
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• pp.15-24
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• 1986

Pressure trasients must deal with safety problem of system. For identification of physical situation that can and method of limiting surges are essential consideration in sucessful design. The finite difference equation by method of characteristics are derived from the governing equation of unsteady flow in a pipe, and solved by using boundary condition derived. A computer program which can simulate general hydraulic system is developed by using finite difference equations and boundary conditions derived. The sumulated resulted by developed computer program are in fair agreement with experiment result.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.14-21
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• 2009

In this paper, a Ka-band 10 W power amplifier module with seven power MMIC bare dies is designed and fabricated using MIC technology which combines multiple MMIC chips on a thin film substrate. Modified Wilkinson power dividers/combiners and CBFGCPW-Microstrip transitions for suppressing resonance and reducing connection loss are utilized for high-gain and high-power millimeter wave modules. A new TTL pulse timing control scheme is proposed to improve output power degradation due to large bypass capacitors in the gate bias circuit. Pulse-mode operation time is extended more than 200 nsec and output power increase of 0.62 W is achieved by applying the proposed scheme to the Ka-band 10 W power amplifier module operating in the pulsed condition of 10 kHz and $5\;{\mu}sec$. The implemented power amplifier module shows a power gain of 59.5 dB and an output power of 11.89 W.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.69-75
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• 2004

This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filers for temperature- and power- insensitive voltage references. The proposed RC low-pass filters improve switching noise performance and reduce reference settling time at heavy R & C loads without conventional off-chip large bypass capacitors. The prototype ABC fabricated in a 0.25 um CMOS occupies the active die area of 2.25 $\textrm{mm}^2$ and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.5
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• pp.90-96
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• 2002

The AC power lines and signal lines of info-communication networks are muted on overhead poles and are exposed to lightning strikes. Due to the potential difference between groundings of the AC power lines and telecommunication lines, the electronic equipments connected to the telecommunication lines can easily be damaged by lightning surges. In this work, in order to develop the reliable ways to protect information and communication facilities from lightning surges, the reliability and performance of surge protective devices were experimentally investigated in actual-sized test circuit. The operation behaviors of surge protective devices against lightning surges from the AC power lines and telecommunication lines and the coordination effects of SPD installation method were evaluated. As a consequence, it was confirmed that the bypass arrester and common grounding system is very effective.

• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.1-12
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• 2010

Recently, processor performance has been improved dramatically. Unfortunately, as the process technology scales down, energy consumption in a processor increases significantly whereas the processor performance continues to improve. Moreover, peak temperature in the processor increases dramatically due to the increased power density, resulting in serious thermal problem. For this reason, performance, energy consumption and thermal problem should be considered together when designing up-to-date processors. This paper proposes three modified filter cache schemes to alleviate the thermal problem in the filter cache, which is one of the most energy-efficient design techniques in the hierarchical memory systems : Bypass Filter Cache (BFC), Duplicated Filter Cache (DFC) and Partitioned Filter Cache (PFC). BFC scheme enables the direct access to the L1 cache when the temperature on the filter cache exceeds the threshold, leading to reduced temperature on the filter cache. DFC scheme lowers temperature on the filter cache by appending an additional filter cache to the existing filter cache. The filter cache for PFC scheme is composed of two half-size filter caches to lower the temperature on the filter cache by reducing the access frequency. According to our simulations using Wattch and Hotspot, the proposed partitioned filter cache shows the lowest peak temperature on the filter cache, leading to higher reliability in the processor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.6
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• pp.719-725
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• 2019

We propose a 2.4-GHz CMOS power amplifier (PA) with a bypass structure to improve the power-added efficiency (PAE) in the low-power region. The primary winding of the output transformer is split into two parts. One of the primary windings is connected to the output of the power stage for high-power mode. The other primary winding is connected to the output of the driver stage for low-power mode. Operation of the high power mode is similar to conventional PAs. On the other hand, the output power of the driver stage becomes the output power of the overall PA in the low power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. We designed the CMOS PA using a 180-nm RFCMOS process. The measured maximum output power is 27.78 dBm with a PAE of 20.5%. At a measured output power of 16 dBm, the PAE is improved from 2.5% to 12.7%.