• Title/Summary/Keyword: 미러어레이

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The 4bit Cell Array Structure of PoRAM and A Sensing Method for Drive this Structure (PoRAM의 4bit 셀 어레이 구조와 이를 동작시키기 위한 센싱 기법)

  • Kim, Jung-Ha;Lee, Sang-Sun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.6 s.360
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    • pp.8-18
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    • 2007
  • In this paper, a 4bit cell way structure of PoRAM and the sensing method to drive this structure are researched. PoRAM has a different operation from existing SRAM and DRAM. The operation is that when certain voltage is applied between top electrode and bottom electrode of PoRAM device we can classify the cell state by measuring cell current which is made by changing resistance of the cell. In the decoder selected by new-addressing method in the cell array, the row decoder is selected "High" and the column decoder is selected "Low" then certain current will flow to the bit-line. Because this current is detect, in order to make large enough current, the voltage sense amplifier is used. In this case, usually, 1-stage differential amplifier using current mirror is used. Furthermore, the detected value at the cell is current, so a diode connected NMOSFET, that is, a device resistor is used at the input port of the differential amplifier to converter current into voltage. Using this differential amplifier, we can classify the cell states, erase mode is "Low" and write mode is "High", by comparing the input value, Vin, that is a product of current value multiplied by resistor value with a reference voltage, Vref.

극소형 MEMS 우주망원경 탑재체 개발 및 탑재

  • Lee, Jik;Kim, Ji-Eun;Na, Go-Un;Nam, Sin-U;Nam, Ji-U;Park, Il-Heung;Seo, Jeong-Eun;Lee, Hye-Yeong;Jeon, Jin-A;Jeong, Su-Min;Jeong, Ae-Ra;Park, Jae-Hyeong;Lee, Chang-Hwan;Park, Yong-Seon;Yu, Hyeong-Jun;Kim, Min-Su;Kim, Yong-Gwon;Yu, Byeong-Uk;Lee, Gyeong-Geon;Jin, Ju-Yeong;G., Garipov;B., Khrenov;P., Klimov
    • Bulletin of the Korean Space Science Society
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    • 2009.10a
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    • pp.47.4-47.4
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    • 2009
  • 초소형전기기계시스템(MEMS: Micro-Electro-Mechanical Systems) 기술로 제작된 마이크로미러 어레이를 장착한 MEMS 우주망원경은 특유의 광시야각 감시, 목표 확인, 확대 및 고속 추적 기능을 가지며 고층대기에서의 초대형 방전현상과 같이 넓은 영역에서 드물게 임의로 일어나는 섬광현상을 관측하기에 최적이다. 러시아 과학위성 Tatiana-2의 주 탑재체로 선정된 극소형 MEMS 우주망원경 MTEL(MEMS Telescope for Extreme Lightning)은 광시야각 감시와 목표 확인을 위한 트리거망원경, 목표 확대와 고속추적을 위한 확대망원경 및 섬광현상의 분광측정을 위한 분광계로 구성되어 있다. 1년간의 개발 및 성능 검증 후 MTEL은 위성탑재를 위한 모든 우주인증 시험을 성공적으로 마쳤다. 현재 MTEL은 Tatiana-2 위성에 탑재되어 있으며, 9월 18일에 우주로 발사되어 1-3년간 800km 궤도를 비행하며 지구 대기에서 발생하는 섬광현상을 관측할 예정이다. 이 발표에서는 MTEL 탑재체의 설계, 제작, 성능 측정 및 calibration 결과를 보고하고, 위성탑재를 위한 진동 및 충격, 열, 진공 및 전자기파 적합성 등의 우주인증 시험 결과 또한 보고한다. 또한 발사 후 과학위성 및 MTEL의 이 발표 때까지의 우주에서의 상황을 보고한다.

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A New Surface Micromachining Technology for Low Voltage Actuated Switch and Mirror Arrays (저전압 구동용 전기스위치와 미러 어레이 응용을 위한 새로운 표면미세가공기술)

  • Park, Sang-Jun;Lee, Sang-Woo;Kim, Jong-Pal;Yi, Sang-Woo;Lee, Sang-Chul;Kim, Sung-Un;Cho, Dong-Il
    • Proceedings of the KIEE Conference
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    • 1998.07g
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    • pp.2518-2520
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    • 1998
  • Silicon can be reactive ion etched (RIE) either isotropically or anisotropically. In this paper, a new micromachining technology combining these two etching characteristics is proposed. In the proposed method, the fabrication steps are as follows. First. a polysilicon layer, which is used as the bottom electrode, is deposited on the silicon wafer and patterned. Then the silicon substrate is etched anisotropically to a few micrometer depth that forms a cavity. Then an PECVD oxide layer is deposited to passivate the cavity side walls. The oxide layers at the top and bottom faces are removed while the passivation layers of the side walls are left. Then the substrate is etched again but in an isotropic etch condition to form a round trench with a larger radius than the anisotropic cavity. Then a sacrificial PECVD oxide layer is deposited and patterned. Then a polysilicon structural layer is deposited and patterned. This polysilicon layer forms a pivot structure of a rocker-arm. Finally, oxide sacrificial layers are etched away. This new micromachining technology is quite simpler than conventional method to fabricate joint structures, and the devices that are fabricated using this technology do not require a flexing structure for motion.

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Four-Channel Differential CMOS Optical Transimpedance Amplifier Arrays for Panoramic Scan LADAR Systems (파노라믹 스캔 라이다 시스템용 4-채널 차동 CMOS 광트랜스 임피던스 증폭기 어레이)

  • Kim, Sang Gyun;Jung, Seung Hwan;Kim, Seung Hoon;Ying, Xiao;Choi, Hanbyul;Hong, Chaerin;Lee, Kyungmin;Eo, Yun Seong;Park, Sung Min
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.9
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    • pp.82-90
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    • 2014
  • In this paper, a couple of 4-channel differential transimpedance amplifier arrays are realized in a standard 0.18um CMOS technology for the applications of linear LADAR(laser detection and ranging) systems. Each array targets 1.25-Gb/s operations, where the current-mode chip consists of current-mirror input stage, a single-to-differential amplifier, and an output buffer. The input stage exploits the local feedback current-mirror configuration for low input resistance and low noise characteristics. Measurements demonstrate that each channel achieves $69-dB{\Omega}$ transimpedance gain, 2.2-GHz bandwidth, 21.5-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -20.5-dBm), and the 4-channel total power dissipation of 147.6-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations. Meanwhile, the voltage-mode chip consists of inverter input stage for low noise characteristics, a single-to-differential amplifier, and an output buffer. Test chips reveal that each channel achieves $73-dB{\Omega}$ transimpedance gain, 1.1-GHz bandwidth, 13.2-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -22.8-dBm), and the 4-channel total power dissipation of 138.4-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations.

A Study of Low-Voltage Low-Power Bipolar Linear Transconductor and Its Application to OTA (저전압 저전력 바이폴라 선형 트랜스컨덕터와 이를 이용한 OTA에 관한 연구)

  • Shin, Hee-Jong;Chung, Won-Sup
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.37 no.1
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    • pp.40-48
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    • 2000
  • 1A novel bipolar linear transconductor and its application to operational transconductance amplifier(OTA) for low-voltage low-power signal processing is proposed. The transconductor consists of a npn differential-pair with emitter degeneration resistor and a pnp differential-pair connected to the npn differential-pair in cascade. The bias current of the pnp differential-pair is used with the output current of the npn differential-pair for wide linearity and temperature stability. The OTA consists of the linear transconductor and a translinear current cell followed by three current mirrors. The proposed transconductor has superior linearity and low-voltage low-power characteristics when compared with the conventional transconductor. The experimental results show that the transconductor with transconductance of 50 ${\mu}S$ has a linearity error of less than ${\pm}$0.06% over an input voltage range from -2V to +2V at supply voltage ${\pm}$3V. Power dissipation of the transconductor was 2.44 mW. A prototype OTA with a transconductance of 25 ${\mu}S$ has been built with bipolar transistor array. The linearity of the OTA was same as the proposed transconductor. The OTA circuit also exhibits a transconductance that is linearly dependent on a bias current varying over four decades with a sensitivity of 0.5 S/A.

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