• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.6
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• pp.94-102
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• 2009

In [1], the authors have proposed a novel scheme to achieve full diversity and to combat the time delays from each relay node, but decode-and-forward (DF) model operation mode puts more processing burden on the relay. In this paper, we not only extend their model into amplify and forward (AF) model proposed in [2],[3], but also propose an efficient decoding algorithm, which is able to order the joint channel coefficients of overall channel consisting of source-relay link and relay-destination link and cancels the previous decoded symbols at the next decoding procedure. The simulation results show that this algorithm efficiently improves its performance achieving 2-3dB gain compared to [1] in high SNR region and also useful to DF achieving more than 3dB gain compared to an original algorithm.

• Journal of Korea Multimedia Society
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• v.13 no.4
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• pp.575-581
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• 2010

With widespread use of the Internet and improvements in streaming media and compression technology, digital music, video, and image can be distributed instantaneously across the Internet to end-users. However, most conventional Digital Right Management are often not secure and not fast enough to process the vast amount of data generated by the multimedia applications to meet the real-time constraints. The SVC offers temporal, spatial, and SNR scalability to varying network bandwidth and different application needs. Meanwhile, for many multimedia services, security is an important component to restrict unauthorized content access and distribution. This suggests the need for new cryptography system implementations that can operate at SVC. In this paper, we propose a new scrambling encryption for reserving the characteristic of scalability in MPEG4-SVC. In the base layer, the proposed algorithm is applied and performed the selective scambling. And it encrypts various MVS and intra-mode scrambling in the enhancement layer. In the decryption, it decrypts each encrypted layers by using another encrypted keys. Throughout the experimental results, the proposed algorithms have low complexity in encryption and the robustness of communication errors.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.27 no.2
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• pp.63-70
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• 2014

Design sensitivity analysis and topology design optimization for a piezoelectric crystal resonator are developed. The piezoelectric crystal resonator is deformed mechanically when subjected to electric charge on the electrodes, or vice versa. The Mindlin plate theory with higher-order interpolations along thickness direction is employed for analyzing the thickness-shear vibrations of the crystal resonator. Thin electrode plates are masked on the top and bottom layers of the crystal plate in order to enforce to vibrate it or detect electric signals. Although the electrode is very thin, its weight and shape could change the performance of the resonators. Thus, the design variables are the bulk material densities corresponding to the mass of masking electrode plates. An optimization problem is formulated to find the optimal topology of electrodes, maximizing the thickness-shear contribution of strain energy at the desired motion and restricting the allowable volume and area of masking plates. The necessary design gradients for the thickness-shear frequency(eigenvalue) and the corresponding mode shape(eigenvector) are computed very efficiently and accurately using the analytical design sensitivity analysis method using the eigenvector expansion concept. Through some demonstrative numerical examples, the design sensitivity analysis method is verified to be very efficient and accurate by comparing with the finite difference method. It is also observed that the optimal electrode design yields an improved mode shape and thickness-shear energy.

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.374-387
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• 2012

In this paper, we implement a new hardware for finding the significant coefficients of a digital hologram and ciphering them using discrete wavelet packet transform (DWPT). Discrete wavelet transform (DWT) and packetization of subbands is used, and the adopted ciphering technique can encrypt the subbands with various robustness based on the level of the wavelet transform and the threshold of subband energy. The hologram encryption consists of two parts; the first is to process DWPT, and the second is to encrypt the coefficients. We propose a lifting based hardware architecture for fast DWPT and block ciphering system with multi-mode for the various types of encryption. The unit cell which calculates the repeated arithmetic with the same structure is proposed and then it is expanded to the lifting kernel hardware. The block ciphering system is configured with three block cipher, AES, SEED and 3DES and encrypt and decrypt data with minimal latency time(minimum 128 clocks, maximum 256 clock) in real time. The information of a digital hologram can be hided by encrypting 0.032% data of all. The implemented hardware used about 200K gates in $0.25{\mu}m$ CMOS library and was stably operated with 165MHz clock frequency in timing simulation.

• Journal of Broadcast Engineering
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• v.19 no.4
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• pp.521-532
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• 2014

ATSC-M/H based hybrid 3DTV, which is one of the service compatible 3DTV system, has considerable quality gap between the left and right views. And CRA(Conditional Replenishment Algorithm) has been proposed to deal with the issue of resolution mismatch and improve the visual quality. In CRA, the disparity vectors of stereoscopic images are estimated. The disparity compensated left view and simply enlarged right view are compared and conditionally selected for generating the enhanced right view. In order to implement CRA, a fast algorithm is strongly required because the disparity vectors need to be obtained at every layer and the complexity of CRA is quite high. In this paper, we adopted SDSP(Small Diamond Search Pattern) instead of full search and predicted the initial position of search pattern by examining the spatio-temporal correlation of disparity vectors and also suggested the SKIP mode to limit the number of processing units. The computer simulation showed that the proposed fast algorithm could greatly reduce the processing time while minimizing the quality degradation of reconstructed right view.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.21 no.5
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• pp.59-69
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• 2011

Since power analysis attack which uses a characteristic that power consumed by crypto device depends on processed data has been proposed, many logics that can block these correlation originally have been developed. DRP logic has been adopted by most of logics maintains power consumption balanced and reduces correlation between processed data and power consumption. However, semi-custom design is necessary because recently design circuits become more complex than before. This design method causes unbalanced design pattern that makes DRP logic consumes unbalanced power consumption which is vulnerable to power analysis attack. In this paper, we have developed new logic style which adds another discharge phase to discharge two output nodes at the same time based on DyCML to remove this unbalanced power consumption. Also, we simulated 1bit fulladder to compare proposed logic with other logics to prove improved performance. As a result, proposed logic is improved NED and NSD to 60% and power consumption reduces about 55% than any other logics.