• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2A
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• pp.188-194
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• 2007

In order to become ubiquitous world, the compatibility of wireless machines has become the significant characteristic of a communication terminal. Thus, SDR is the most necessary technology and standard. However, among the environment which has different communication protocol, it's difficult to make a terminal with only hardware using ASIC or SoC. This paper suggests the processor that can accelerate several communication protocol. It can be connected with main-processor, and it is specialized PHY layer of network The C-program that is modeled with the wireless protocol IEEE802.11a and IEEE802.11b which are based on widely used modulation way; OFDM and CDM is compiled with ARM cross compiler and done simulation and profiling with Simplescalar-Arm version. The result of profiling, most operations were Viterbi operations and complex floating point operations. According to this result we suggested a co-processor which can accelerate Viterbi operations and complex floating point operations and added instructions. These instructions are simulated with Simplescalar-Arm version. The result of this simulation, comparing with computing only one ARM core, the operations of Viterbi improved as fast as 4.5 times. And the operations of complex floating point improved as fast as twice. The operations of IEEE802.11a are 3 times faster, and the operations of IEEE802.11b are 1.5 times faster.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.735-745
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• 2001

Processors require both intensive and extensive functional verification in their design phase due to their general purpose. The proposed random vector verification method for embedded control RISC cores meets this goal by contributing assistance for conventional methods. The proposed method proved its effectiveness during the design of CalmRISCTM-32 developed by Yonsei Univ. and Samsung. It adopts a cycle-accurate instruction level simulator as a reference model, runs simulation in both the reference and the target HDL and reports errors if any difference is found between them. Consequently, it successfully covers errors designers easily pass over and establishes other new error check points.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2006.05a
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• pp.119-123
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• 2006

본 논문에서는 마이크로프로세서의 기능을 수행하는 데 필수적이며 사용빈도가 높은 총 64개의 명령어를 정의한 후 이를 처리할 데이터패스를 구성해 스테이트 머쉰으로 제어하는 방식으로 실용적 8비트 마이크로프로세서를 VHDL로 설계를 하고 FPGA로 구현했다. 통상 마이크로프로세서 관련 논문에서는 기능적 시뮬레이션까지만 했거나, 인터럽트 기능이 없든지, 하드웨어로 구현을 하지 않았거나, 또는 개발 관련 내용이 자세히 제시되지 않았었다. 본 논문에서는 데이터 이동, 논리, 가산 연산뿐만 아니라 분기, 점프 연산도 실행할 수 있도록 해 연산 및 제어용도에 적합하도록 하였고, 스택, 외부 인터럽트 기능까지도 지원하도록 해 그 자체로서 완전한 실용적 마이크로프로세서가 되도록 하였다. 또한 프로그램 ROM까지도 칩 안에 넣어 전체 마이크로프로세서를 단일 칩으로 구현하였다. 타이밍 시뮬레이션으로 검증 후 제작 과정을 통해, 설계된 마이크로프로세서가 정상적으로 동작함을 확인하였다. Altera MAX+.PLUS II 통합개발환경 하에서 EP1K50TC144-3 FPGA 칩으로 구현을 하였고 최대 동작주파수는 9.39MHz까지 가능했고 사용한 로직 엘리먼트의 개수는 2813개로서 논리 사용률은 97%이었다.

• Journal of the Korea Society of Computer and Information
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• v.24 no.11
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• pp.1-9
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• 2019

In this paper, we propose a Small Active Command scheme which reduces the power consumption of the command bus to DRAM. To do this, we target the ACTIVE command, which consists of multiple packets, containing the row address that occupies the largest size among the addresses delivered to the DRAM. The proposed scheme identifies frequently referenced row addresses as Hot pages first, and delivers index numbers of small caches (tables) located in the memory controller and DRAM. I-ACTIVE and I-PRECHARGE commands using unused bits of existing DRAM commands are added for index number transfer and cache synchronization management. Experimental results show that the proposed method reduces the command bus power consumption by 20% and 8.1% on average in the close-page and open-page policies, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.7
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• pp.3152-3159
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• 2012

This paper presents the new instruction-level power model for an asynchronous processor. Until now, the various power models for estimating the power dissipation of embedded processor in SoC are proposed. Since all of them are target to the synchronous processors, the accuracy is questionable when we apply those power models to the asynchronous processor in SoC. To solve this problem, we present new power model for an asynchronous processor by reflecting the behavioral features of an asynchronous circuit. The proposed power model is verified using an implementation of asynchronous processor, A8051. The simulation results of the proposed model is compared with the measurement result of gate-level synthesized A8051. The proposed power model shows the accuracy of 90.7% and the simulation time for estimation the power consumption was reduced to 1,900 times.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.6
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• pp.1-11
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• 2004

Modern processors achieve high performance exploiting avaliable Instruction Level Parallelism(ILP) by using speculative technique such as branch prediction. Traditionally, branch direction can be predicted at very high accuracy by 2-level predictor, and branch target address is predicted by Branch Target Buffer(BTB). Except for indirect branch, each of the branch has the unique target, so its prediction is very accurate via BTB. But because indirect branch has dynamically polymorphic target, indirect branch target prediction is very difficult. In general, the technique of branch direction prediction is applied to indirect branch target prediction, and much better accuracy than traditional BTB is obtained for indirect branch. We present a new indirect branch target prediction scheme which combines a indirect branch instruction with its data dependent register of the instruction executed earlier than the branch. The result of SPEC benchmark simulation which are obtained on SimpleScalar simulator shows that the proposed predictor obtains the most perfect prediction accuracy than any other existing scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.74-84
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• 2000

This paper deals with procedures for design and implementation of a DSP, which is compatible with TMS320C30 DSP. CBS(Cycle Based Simulator) is developed to study the architecture of the target DSP. The simulator gives us detailed information such as function block operation, control signal values, register condition, bus and memory values when a instruction is being carried out. RTL design is carried out by VHDL. Logic simulation and hardware emulation are employed to verify proper operation of the design. The DSP is fabricated with 0.6${\mu}m$ CMOS technology. The Chip has 450,000 gates complexity, $9{\times}9mm^2$ area, 20 MIPS operation speed. It is confirmed by running 109 instructions out of 114 instructions and 13 kinds of algorithm that the developed DSP has compatibility with TMS320C30.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.29-42
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• 1990

In this paper, We use the APL as IDL when simulation a 16-bit SIP. It was possible for IDL to represent and describe a structure of a H/W which other HDL have not. Because We partitioned whole system to various modules when desingning processor, We adpoted a direct decoding method. A designed each modules are executed according to 12-bit control word was inputed through experimental framework, Which were composed to symbolized instructions. In here, By setting instruction codes of the SIP using binary code, We composed instruction format and assembler instruction, and verified the SIP behaviour that try to implement by entering a presented instruction set through experimental framework. In a presented SIP, Because inputing program are a symbolized language, Designer and user will easily understand behaviour of system. Especially, Because we can immediatly specify a unit function within SIP, We will use variously and easily the library cell.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.497-502
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• 2002

Conditional branches can severely limit the performance of instruction level parallelism by causing branch penalties. 2-level adaptive branch predictors were developed to get accurate branch prediction in high performance superscalar processors. Although 2 level adaptive branch predictors achieve very high prediction accuracy, they tend to be very costly. In this paper, set-associative cached correlated 2-level branch predictors are proposed to overcome the cost problem in conventional 2-level adaptive branch predictors. According to simulation results, cached correlated predictors deliver higher prediction accuracy than conventional predictors at a significantly lower cost. The best misprediction rates of global and local cached correlated predictors using set-associative caches are 5.99% and 6.28% respectively. They achieve 54% and 17% improvements over those of the conventional 2-level adaptive branch predictors.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.11
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• pp.601-612
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• 2001

In superscalar processors, value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction in order to exploit instruction level parallelism(ILP). A value predictor looks up the prediction table for the prediction value of an instruction in the instruction fetch stage, and updates with the prediction result and the resolved value after the execution of the instruction for the next prediction. However, as the instruction fetch and issue rates are increased, the same instruction is likely to fetch again before is has been updated in the predictor. Hence, the predictor looks up the stale value in the table and this mostly will cause incorrect value predictions. In this paper, a stride value predictor with the capability of speculative updates, which can update the prediction table speculatively without waiting until the instruction has been completed, is proposed. Also, the performance of the scheme is examined using Simplescalar simulator for SPECint95 benchmarks in which our value predictor is added.