• KIPS Transactions on Software and Data Engineering
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• v.5 no.12
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• pp.641-652
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• 2016

This paper proposes a method to generate test scripts in an automatic manner, based on checklist used for testing embedded systems in the fields. The proposed method can reduce the mistakes which may be introduced during manual generation. In addition, it can generate test scripts to test various mode combinations, which is not possible to be tested by the typical checklist. The test commands in a checklist are transformed into a test script suit referencing the signal values defined in a test command dictionary. In addition, the method to generate test scripts in sequential, double permutation and random manners is proposed useful to test the inter-operations between modes, a series of operations for a specific behavior. The proposed method is implemented and the feasibility is shown through the experiments.

• Journal of the Korea Society of Computer and Information
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• v.17 no.11
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• pp.1-10
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• 2012

In this paper, the extension of the addressing mode in the 16-bit Thumb instruction set architecture is proposed to improve the performance of 16-bit Thumb code. The key idea of the proposed approach is the introduction of new addressing modes for more frequent instructions by using the saved bits from the reduction of the register fields in less frequently used instructions. The proposed approach adopts efficient addressing modes from the 32-bit ARM architecture, which is the superset of the 16-bit Thumb architecture. To speed up access to a data list, scaled register offset addressing mode and post-indexed addressing mode are introduced for load and store instructions. Experiments show that the proposed approach improves performance by an average of 8.5% when compared to the conventional approach.

• KIPS Transactions on Software and Data Engineering
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• v.6 no.5
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• pp.245-256
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• 2017

This paper proposes a method to generate test scripts for testing embedded system in an easy manner by using hierarchical checklist. In the proposed method, a checklist is constructed with event, component and command dictionaries. And the test scripts are hierarchically generated based on the dictionaries. Since the physical layer of system input becomes abstract with component layer and event layer by virtue of the hierarchy, It is possible to generate test scripts without complicated system input information. It is easy to generate test scripts for embedded systems with similar inputs using the highly reusable dictionaries. The effectiveness of the proposed method is demonstrated with experiments.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.04a
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• pp.49-52
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• 2012

컴파일러의 명령어 스케줄링 기법이 제대로 동작하기 위해서는 자료 의존성 그래프가 필요하다. 본 논문에서는 워크리스트 알고리즘을 사용한 자료 의존성 그래프 생성 구현에 대하여 설명하고자 한다.

• KIISE Transactions on Computing Practices
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• v.23 no.8
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• pp.498-503
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• 2017

SIMD (Single Instruction Multiple Data) is a representative parallelization architecture that processes multiple data loaded in a SIMD register with a single instruction. Quicksort is a sorting algorithm that picks an element as a pivot from the array and reorders the array such that all elements having the values less than the pivot value are located in the left side on the pivot as well as all elements having the value greater than the pivot value are located in the right side on the pivot and then the algorithm performs the same task on both sublist recursively. In this paper, we propose an efficient Quicksort algorithm applying the SIMD instructions which minimally invokes conditional branches to avoid the performance degradation incurred by branch misprediction in a pipeline architecture. In addition, we improve the performance of the Quicksort algorithm by fetching data into a SIMD register as a byte unit to apply VBP (Vertical Bit Parallel) and the early pruning technique.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.11 no.1
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• pp.61-69
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• 2002

This paper describes a converting algorithm between programmable languages of a software PLU. It is based on IEC 61131-3 standard and PC. The proposed control logic is designed by the software model and common element with data type, variables, POUs(program organization unit) and execution control unit commonly used within programmable languages of IEC 61131-3 Standard. The generation method of object file is proposed on five programmable language based on IEC 61131-3. It is represented as fo11ows; 1) the generation method using conversion algorithm from LD to IL with FBD(function block diagram), 2) the generation method using f code generation algorithm from SFC using the SFC execution sequence with FBD and ST(structured text). The proposed control logic generator was implemented by Visual C++ 6.0 and MFC on MS-windows NT 4.0.

• The Journal of Korean Association of Computer Education
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• v.18 no.3
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• pp.49-57
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• 2015

The purpose of this study is to provide considerations through investigation and analysis about non-computer major learners' difficulties in computational thinking education. In recent, the importance of human resources development in convergence based on computational thinking is increasing internationally and a Korean university is selecting CT as a mandatory subject. I taught CT with Scratch at C university in Seoul for two semesters in 2014 and investigated and analyzed what difficulties non-Computer majors felt in the process of CT education. The result showed they felt the following some difficulties in order: the concept of variable and list; to think a idea and implement it; which commands should be selected. The pleasure and the interest can be apply to decrease difficulty, because they affect self-programming ability and self-CT capability each other statistically. Although Scratch is an easy and an intuitive programming language, it is needed to consider to provide appropriate learning time to student for using and applying commands.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2001.04a
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• pp.171-176
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• 2001

This paper describes the methodology of an IEC 1131-3-based control logic generator for the control system design and converting algorithm between programmable languages. The proposed control logic generator is generated based on the software model and common element with data type, variables, POUs(program organization unit) and execution control unit commonly used within programmable languages of IEC 1131-3 Standard. The generation method of object file was proposed on five programmable language based on IECI 131-3. The generation method of object file is represented as following; 1) the generation method using conversion algorithm from LD to IL with FBD(function block diagram), 2) the generation method using C code generation algorithm from SFC using the SFC execution sequence with FBD and ST(structured text). The proposed control logic generator was implemented by Visual C++ and MFC on MS-windows NT 4.0

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.