• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.380-380
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• 2012

유기물 나노 복합체는 고집적/저전력/플렉서블 특성을 가지는 초고효율 비휘발성 메모리 소자를 제작하는데 많은 이점을 가지고 있어, 차세대 비휘발성 메모리 소자에 사용되는 소재로 매우 각광받고 있다. 그 중, WORM 특성을 가지는 메모리 소자는 1회 쓰기 후 수많은 읽기가 가능하기 때문에, 그 효율성이 매우 뛰어나 이목을 끌고 있다. 유기물 나노 복합체 중에서, poly(3-hexylthiophene) (P3HT)는 화학적/전기적 안정성과 전하의 이동도 특성이 뛰어나기 때문에 전자 소자에 응용하려는 연구가 활발히 진행되고 있다. 본 연구에서는 $P_3HT$ 고분자를 polymethylmethacrylate(PMMA) 고분자에 분산시킴으로써, 상태를 기억하는 저장 매체로 사용하였다. 본 연구의 소자를 제작하기 위하여 약 9 : 1 비율을 가지는 PMMA 와 $P_3HT$를 용매인 클로로벤젠에 녹여 용액을 준비하였다. Indium Tin Oxide (ITO)가 코팅된 glass를 화학적 처리를 통해 청결하게 만든 후, PMMA와 $P_3HT$가 용해되어 있는 용액을 스핀 코팅 방법으로 박막을 형성하였다. PMMA 속에 $P_3HT$가 분산되어 있는 활성층 위에 상부 전극으로 Al을 열 증착 방식을 통하여 형성하였다. 제작된 WORM 특성을 갖는 유기물 나노 복합체 플렉서블 소자의 메모리 효과에 대한 분석을 위하여, -5V에서 5V까지 전압을 인가하여 전류-전압 특성을 측정하였다. 초기 낮은 전도도 (OFF 상태, 10-10A에서 10-4A)를 유지하다가, 쓰기 전압을 1회 가해준 후부터는 높은 전도도 (ON 상태, 10-5A 에서 10-2A)를 유지하는 특성을 관측하였다. 또한 WORM 특성을 갖는 메모리 소자로써의 능력을 보여주기 위하여, 1회 쓰기 전압 후 읽기 전압인 1V를 인가하여 높은 전도도 상태에 대한 상태 유지 능력을 측정하였고, 전하 수송 메커니즘을 규명하기 위하여 피팅 모델을 통해 설명하였다.

• Smart Media Journal
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• v.3 no.1
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• pp.33-38
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• 2014

Even though the performance of microprocessor is improved continuously, the performance improvement of computing system becomes hard to increase, in order to some drawbacks including increased power consumption. To solve the problem, general-purpose computing on graphics processing units(GPGPUs), which execute general-purpose applications by using specialized parallel-processing device representing graphics processing units(GPUs), have been focused. However, the characteristics of applications related with graphics is substantially different from the characteristics of general-purpose applications. Therefore, GPUs cannot exploit the outstanding computational resources sufficiently due to various constraints, when they execute general-purpose applications. When designing GPUs for GPGPU, memory system is important to effectively exploit the GPUs since typically general-purpose applications requires more memory accesses than graphics applications. Especially, external memory access requiring long latency impose a big overhead on the performance of GPUs. Therefore, the GPU performance must be improved if hierarchical memory architecture which can reduce the number of external memory access is applied. For this reason, we will investigate the analysis of GPU performance according to hierarchical cache architectures in executing various benchmarks.

• Geophysics and Geophysical Exploration
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• v.19 no.3
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• pp.145-152
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• 2016

We used graphics processing units for an efficient time-domain 3D wave propagation modeling. Since graphics processing units are designed for massively parallel processes, we need to optimize the calculation and memory management to fully exploit graphics processing units. We focused on the memory management and examined the performance of programs with respect to the memory management methods. We also tested the effects of memory transfer on the performance of the program by varying the order of finite difference equation and the size of velocity models. The results show that the memory transfer takes a larger portion of the running time than that of the finite difference calculation in programs transferring whole 3D wavefield.

• The KIPS Transactions:PartD
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• v.14D no.7
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• pp.719-726
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• 2007

Recently, NAND flash memory has been used for a storage device in various mobile computing devices such as MP3 players, mobile phones and laptops because of its shock-resistant, low-power consumption, and none-volatile properties. However, due to the very distinct characteristics of flash memory, disk based systems and applications may result in severe performance degradation when directly adopting them on flash memory storage systems. Especially, when a B-tree is constructed, intensive overwrite operations may be caused by record inserting, deleting, and its reorganizing, This could result in severe performance degradation on NAND flash memory. In this paper, we propose an efficient buffer management scheme, called IBSF, which eliminates redundant index units in the index buffer and then delays the time that the index buffer is filled up. Consequently, IBSF significantly reduces the number of write operations to a flash memory when constructing a B-tree. We also show that IBSF yields a better performance on a flash memory by comparing it to the related technique called BFTL through various experiments.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.177-185
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• 2005

NAND-type flash memory is becoming increasingly popular as a large data storage for mobile computing devices. Since flash memory is an order of magnitude more expensive than magnetic disks, data compression can be effectively used in managing flash memory based storage systems. However, compressed data management in NAND-type flash memory is challenging because it supports only page-based I/Os. For example, when the size of compressed data is smaller than the page size. internal fragmentation occurs and this degrades the effectiveness of compression seriously. In this paper, we present an efficient flash compression layer (FCL) for NAND-type flash memory which stores several small compressed pages into one physical page by using a write buffer Based on prototype implementation and simulation studies, we show that the proposed scheme offers the storage of flash memory more than $140\%$ of its original size and expands the write bandwidth significantly.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.1
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• pp.70-74
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• 2010

As the storage capacity of the flash memories increased portable devices began to store mass amount of multimedia data on flash memory. Therefore, there has been a need for an effective data management scheme by indexing structure. Among many indexing schemes, M-tree is well known for it's suitability for multimedia data with high dimensional matrix space. Since flash memories have writing operation restriction, there is a performance limitation in indexing scheme with frequent write operation. In this paper, a new node split method with reduced write operation for m-tree indexing scheme in flash memory is proposed. According to experiments the proposed method reduced the write operation to about 7% of the original method. The proposed method will effectively construct an indexing structure for multimedia data in flash memories.

• KIPS Transactions on Software and Data Engineering
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• v.5 no.12
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• pp.623-634
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• 2016

Most of existing frequent pattern mining methods address time efficiency and greatly rely on the primary memory. However, in the era of big data, the size of real-world databases to mined is exponentially increasing, and hence the primary memory is not sufficient enough to mine for frequent patterns from large real-world data sets. To solve this problem, there are some researches for frequent pattern mining method based on disk, but the processing time compared to the memory based methods took very time consuming. There are some researches to improve scalability of frequent pattern mining, but their processes are very time consuming compare to the memory based methods. In this paper, we present PPFP as a novel disk-based approach for mining frequent itemset from big data; and hence we reduced the main memory size bottleneck. PPFP algorithm is based on FP-growth method which is one of the most popular and efficient frequent pattern mining approaches. The mining with PPFP consists of two setps. (1) Constructing an IFP-tree: After construct FP-tree, we assign index number for each node in FP-tree with novel index numbering method, and then insert the indexed FP-tree (IFP-tree) into disk as IFP-table. (2) Mining frequent patterns with PPFP: Mine frequent patterns by expending patterns using stack based PUSH-POP method (PPFP method). Through this new approach, by using a very small amount of memory for recursive and time consuming operation in mining process, we improved the scalability and time efficiency of the frequent pattern mining. And the reported test results demonstrate them.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.3
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• pp.13-19
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• 2016

Spark, an in-memory big-data processing framework is popular to use for real-time processing workload. Spark can store all intermediate data in the cluster memory so that Spark can minimize I/O access. However, when the resident memory of workload is larger that the physical memory amount of the cluster, the total performance can drop dramatically. In this paper, we analyse the factors of bottleneck on PageRank Application that needs many memory through experiment, and cluster the Spark with Tachyon File System for using memory to solve the factor of bottleneck and then we improve the performance about 18%.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.05c
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• pp.1575-1578
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• 2003

이동통신 기술의 발달로 인하여 무선 이동 기기의 사용이 보편화되면서 LBS(Location Based System)의 요구가 나날이 증대되고 있다. 이와 같은 위치 기반 서비스에서 클라이언트인 이동체들은 일정한 보고 주기를 가지고 서버에 위치 데이터를 보고하게 되는데, 빈번한 보고 데이터를 실시간으로 처리하기 위해서 서버에서는 메인 메모리 DBMS를 유지하는 것이 필요하다. 기존에 제시된 메인 메모리 색인으로는 T-tree 가 있는데, 이는 1차원 데이터를 위한 것이므로 이동체 데이터베이스 환경에 적합하지 못하다. 그리고, 디스크 기반의 다차원 색인으로는 R-tree 계열이 있는데, 이는 메인 메모리에서 효율적인 사용을 보장하지 못한다. 이 논문에서는 이동체 데이터베이스 환경에 적합한 메인 메모리 색인을 고려함에 있어서, 기존의 디스크 기반의 다차원 색인으로 가장 널리 알려진 R-tree 계열의 색인을 메인 메모리에 적재 후 메인 메모리 환경에서 성능에 영향을 주는 요소를 실험을 통하여 제시한다. 실험은 메인 메모리에서는 간단한 알고리즘을 사용하는 것이 성능에 좋고, 삽입 시에는 삽입할 노드를 찾기 위해서 비교하는 엔트리의 수가, 검색 시에는 노드간의 중첩으로 인하여 비교하는 노드의 수와 엔트리의 수가 성능에 영향을 주는 요소임을 보여준다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.72-79
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• 2003

Due to the improvements in circuit design technique and manufacturing technique, complexity of a circuit is growing along with the demand for memories with large capacities. Likewise, as a memory capacity gets larger, testing gets harder and testing cost increases, and testing process in chip development gets larger as well. Therefore, a research on an effective test algorithm to improve the chip yield rate in a short time period is becoming an important task. This paper proposes an effective, March C-algorithm based, test algorithm that can also be applied to a dual-port memory since it considers all the fault types, which can be occurred in a single-port as well as in a dual-port memory, without increasing the test length.