• Journal of the Korea Society of Computer and Information
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• v.12 no.6
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• pp.139-146
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• 2007

A hard disk. which can be classified as an external storage is usually capacious and economical. In spite of the attractive characteristics and efforts on the performance improvement, however, the operation of the hard disk is apparently slower than a processor and the advancement has also been slowly conducted since it is based on mechanical process. On the other hand. the advancement of the processor has been drastically performed as semiconductor technology does. So, disk I/O sub-system becomes bottleneck of computer systems' performance. For this reason. the research on disk I/O sub-system is in progress to improve computer systems' performance. In this paper, we proposed multi-level LRU scheme and then apply it to the computer systems with buffer cache and disk cache. By applying the proposed scheme to computer systems. the average access time to ask blocks can be decreased. The efficiency of the proposed algorithm was verified by simulation results.

• Journal of the Korea Society of Computer and Information
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• v.25 no.7
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• pp.1-8
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• 2020

In this paper, we present an implementation of high speed image data transfer using XDMA for a video signal generation / acquisition device developed as a military test equipment. The technology proposed in this study obtains efficiency by replacing the method of copying data using the system buffer in the kernel area with the transmission and reception through the DMA engine in the FPGA. For this study, the device was developed as a PXIe platform in consideration of life cycle, and performance was maximized by using a low-cost FPGA considering mass productivity. The video I/O board implemented in this paper was tested by changing the AXI interface clock frequency and link speed through the existing memory copy method. In addition, the board was constructed using the DMA engine of the FPGA, and as a result, it was confirmed that the transfer speed was increased from 5~8Hz to 140Hz. The proposed method will contribute to strengthening defense capability by reducing the cost of device development using the PXIe platform and increasing the technology level.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.10
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• pp.37-44
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• 1999

This paper report the implementation results of Monte Carlo numerical calculation for ion distributions in plasma dry etching chamber and of the surface evolution simulator using cell removal method for topographical evolution of the surface exposed to etching ion. The energy and angular distributions of ion across the plasma sheath were calculated by MC(Monte Carlo) algorithm. High performance MPP(Massively Parallel Processing) algorithm developed in this paper enables efficient parallel and distributed simulation with an efficiency of more than 95% and speedup of 16 with 16 processors. Parallelization of surface evolution simulator based on cell removal method reduces simulation time dramatically to 15 minutes and increases capability of simulation required enormous memory size of 600Mb.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.8-16
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• 2010

NAND multilevel cell (MLC) flash memory is widely issued because it can increase the capability of storage by storing two or more bits to a single cell. However if a number of levels in a cell increases, some physical features like cell to cell interference result cell voltage shift and it is known that a VT shift is unidirectional. To reduce errors by the effects, we can consider error correcting codes(ECC) or signal processing methods. We focus signal processing methods for the cell to cell interference voltage shift effects and propose the algorithms which reduce the effects of the voltage shift by estimating it and making level read voltages be adaptive. These new algorithms can be applied with ECC at the same time, therefore these algorithms are efficient for MLC error correcting ability. We show the bit error rate simulation results of the algorithms and compare the performance of the algorithms.

• Journal of Digital Contents Society
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• v.3 no.1
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• pp.101-111
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• 2002

Lately development of network around Internet expands range of data traffic to multimedia information, and so for the guarantee of multimedia services end-to-end QoS(Quality of Service) must service because comparing with existing Internet service can not support For satisfying those QoS requirements, network have to guarantee not only network on parameter, such as delay, jitter, throughput but also system resources like CPU utilization, memory usage. Therefore it is urgent to develop QoS based middleware to distribute multimedia data and maximize network utilization in the limited resource environment. And it must be necessary of network to provide end-to-end QoS(Quality of Service) for multimedia applications. Multimedia applications want that QoS which satisfy their own service properties be guaranteed Then, We must analyze those necessary QoS requirements md define QoS parameter which specify as two viewpoint, user's and network's perspective. Therefore network provider supplying network for usual user and university, enterprise must want to find about their own network performance and problem. It is essential for network manager to want to use a tool like this. On the basis of technique about QoS test-bed in the AIM network, We studied on the method of QoS measurement and management about end-to-end connection in the Internet. We measured network status about end-to-end connection and analyze the result of performance.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.2
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• pp.241-251
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• 2015

In public-key cryptographic system based on finite field arithmetic, it is very important to challenge for implementing high speed operation. In this paper, we focused on 8-bit ATmega128 processor and concentrated on enhancing efficiency of reduction operation which uses irreducible polynomial $f(x)=x^{271}+x^{207}+x^{175}+x^{111}+1$ and $f(x)=x^{193}+x^{145}+x^{129}+x^{113}+1$. We propose optimized reduction algorithms which are designed to reduce repeated memory accesses by calculating final reduced values of Fast reduction. There are 53%, 55% improvement when proposed algorithm is implemented using assembly language, compare to previous Fast reduction algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1573-1581
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• 2006

To utilize actively the agent which is one of the elements of revitalization of Agro-Foods Mobile I-commerce, an essential prerequisite is agent security. IF using partial PKI(Public Key Infrastructure)-based confirmation mechanism providing security for the agent, the size of agent is becoming larger, the result of the transmission speed is slow, and the confirmation speed is tardy as well because of performing calculation of public keys such as RSA and needing linkage with the CA for the valid examination of certificates. This paper suggests a mechanism that can cross certification and data encryption of each host in the side of improving the problems of key distribution on agent by shaping key chain relationship. This mechanism can guarantee the problem of ky distribution by using agent cipher key(ACK) module and generating random number to fit mobile surroundings and to keep the secret of the agent. Suggested mechanism is a thing that takes into consideration security and efficiency to secure agent for the revitalization of M-Commerce, and is a code skill to make the agent solid and is a safe mechanism minimizing the problems of memory overflow.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.259-266
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM (or SRAM) cell. Layout pitch of one-bit-wide logic is Identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1) simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• The KIPS Transactions:PartB
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• v.10B no.7
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• pp.795-802
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• 2003

To live autonomously, intelligent agents such as robots or virtual characters need ability that recognizes given environment, and learns and chooses adaptive actions. So, we propose an action selection/learning mechanism in intelligent agents. The proposed mechanism employs a hybrid system which integrates a behavior-based method using the reinforcement learning and a cognitive-based method using the symbolic learning. The characteristics of our mechanism are as follows. First, because it learns adaptive actions about environment using reinforcement learning, our agents have flexibility about environmental changes. Second, because it learns environmental factors for the agent's goals using inductive machine learning and association rules, the agent learns and selects appropriate actions faster in given surrounding and more efficiently in extended surroundings. Third, in implementing the intelligent agents, we considers only the recognized states which are found by a state detector rather than by all states. Because this method consider only necessary states, we can reduce the space of memory. And because it represents and processes new states dynamically, we can cope with the change of environment spontaneously.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1218-1226
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• 1999

In decoding the turbo codes, the sliding window BCJR algorthm, derived from the BCJR algorithm, permits a continuous decoding of the coded sequence without requiring trellis fermination of the constituent codes and uses reduced memory span. However, the number of computation required is greater than that of BCJR algorithm and no study on the effect of the window length has been reported. In this paper, we propose an eddicient sliding window type scheme which maintains the advantages of the conventional sliding window algorithm, reduces its computational burdens, and improves is BER performance. A guideline is first presented to determine the proper window length and then a computationally efficient sliding window BCJR algorithm is obtained by allowing the window to be forwarded in multi-step. Simulation results show that the proposed scheme outperforms the conventional sliding window BCJR algorithm with reduced complexity. It gains 0.1dB SNR improvements over the conventional method for the constraint length 3 and BER $10^{-4}$