• Korean Chemical Engineering Research
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• v.47 no.1
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• pp.1-10
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• 2009

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional chip cannot be a solution for the enhancement of the semiconductor chip technology due to an increase in RC delay among interconnects. To address this problem, a new technology - "3 dimensional (3D) IC chip stack" - has been emerging. For the integration of the technology, several new key unit processes (e.g., silicon through via, wafer thinning and wafer alignment and bonding) should be developed and much effort is being made to achieve the goal. As a result of such efforts, 4 and 8 chip-stacked DRAM and NAND structures and a system stacking CPU and memory chips vertically were successfully developed. In this article, basic theory, configurations and key unit processes for the 3D IC chip integration, and a current tendency of the technology are explained. Future opportunities and directions are also discussed.

• Journal of KIISE
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• v.42 no.4
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• pp.522-529
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• 2015

Ever since the R-tree was proposed to index multi-dimensional data, many efforts have been made to improve its query performances. One common trend to improve query performance is to parallelize query processing with the use of multi-core architectures. To this end, a GPU-base R-tree has been recently proposed. However, even though a GPU-based R-tree can exhibit an improvement in query performance, it is limited in its ability to handle large volumes of data because GPUs have limited physical memory. To address this problem, we propose MGR-tree (Multi-GPU R-tree), which can manage large volumes of data by dividing nodes into multiple GPUs. Our experiments show that MGR-tree is up to 9.1 times faster than a sequential search on a GPU and up to 1.6 times faster than a conventional GPU-based R-tree.

• Journal of Korea Society of Industrial Information Systems
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• v.13 no.5
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• pp.117-123
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• 2008

In this paper, we develop MPEG-4 AAC streaming player on embedded Linux processor such as mobile terminals. Moreover we show the experimental results that the player preforms the decoding processes of MPEG-4 AAC data effectively. MPEG-4 AAC technology supports a wide range encoding rates and high sound quality so it is appropriate to adopt various applications. In particular, the need in the development of the application of audio data increases according to significantly increase in devices used in mobile environments, such as cell phones and PDAs. In this environment, it is necessary to optimize the decoding processes to the ability of the terminal hardware in order to play audio data without delays. We also implement the decoding module to optimize the processor capabilities and make the player to decode and play streaming audio data from streaming server.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.233-233
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• 2012

나노입자가 가지는 고유한 특성이 부각되면서 이를 소자 특성 향상에 응용하고자 하는 연구가 집중적으로 이루어지고 있다. 박막에 포함된 나노입자는 메모리, 고효율 박막형 태양전지 등에 이용될 수 있는 가능성을 보여주었으며, 나노입자에 기반 하는 소자 제조에 관한 연구가 이루어지면서 플라즈마 내 발생하는 나노입자를 이용하여 패터닝 등에 적용하고자 하는 연구가 국내외에서 활발히 이루어지고 있다. 특히 플라즈마에서 발생하는 나노입자는 플라즈마 내 전기적 및 화학적 특징으로 인해 다른 입자 제조 공정과 달리 응집이 없는 균일한 입자를 제조할 수 있다. 이러한 플라즈마 내 발생 입자를 응용하기 위해서는 각각의 응용 분야에 적합한 입경 분포 제어가 요구된다. 하지만 입자 합성 시 크기분포 특성에 관한 연구는 기존의 포집 및 전자현미경을 이용한 방법으로 실시간으로 분석하기에는 한계가 있다. 따라서 본 연구에서는 저압에서 실시간으로 나노입자 분포를 측정할 수 있는 PBMS (particle beam mass spectrometer)를 이용하여, PECVD (plasma enhanced chemical vapor deposition)의 입자 생성 조건에 따라 continuous, pulse, dual pulse로 분류되는 공정 조건에서 생성되는 입자의 크기 분포를 측정하였다. 또한 그 결과를 기존의 동일한 조건에서 포집 후 SMPS (scanning mobility particle sizer)와 전자 현미경을 이용하여 분석한 결과와 비교하였다. 실리콘 나노 입자의 측정은 PBMS 장비의 전단 부분을 PECVD 장치 내부에 연결하여 진행하였다. PECVD를 이용한 실리콘 나노입자 형성의 주요 변수는 RF pulse, 가스(Ar, SiH4, H2)의 유량, Plasma power, 공정 압력 등이 있으며 각 변수를 조절하여 공정 환경을 구성하였다. 결론적으로 본 연구를 통하여 PECVD를 이용해 각각의 공정 환경에서 생성되는 실리콘 나노입자의 실시간 입경 분포 분석을 PBMS로 수행하는 것에 신뢰성이 있음을 알 수 있었으며, 그 경향을 확인할 수 있었다. 추후 지속적 연구에 의해 변수에 따른 나노입자 생성을 데이터베이스화 하여 요구되는 응용분야에 적합한 특성을 가지는 나노입자를 형성하는 조건을 정립 하는데 중요한 역할을 할 것을 기대할 수 있다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.2
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• pp.57-64
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• 2009

This paper presents the hardware implementation of the pyramidal KLT(Kanade-Lucas-Tomasi) feature tracker. Because of its high computational complexity, it is not easy to implement a real-time KLT feature tracker using general-purpose processors. A hardware implementation of the pyramidal KLT feature tracker using FPGA(Field Programmable Gate Array) is described in this paper with emphasis on 1) adaptive adjustment of threshold in feature extraction under diverse lighting conditions, and 2) modification of the tracking algorithm to accomodate parallel processing and to overcome memory constraints such as capacity and bandwidth limitation. The effectiveness of the implementation was evaluated over ones produced by its software implementation. The throughput of the FPGA-based tracker was 30 frames/sec for video images with size of $720{\times}480$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2032-2041
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• 1998

In this work, we propose a novel bit allocation method that is to minimize overall distortions subject ot the bit rate constraint. We partition the original bitallocation problem into 'macroblock level bit allocation' problems that can be solved by conventional Lagrangian mutiplier methods and a 'frame level bit allocation' problem. To tackle the frame level problem, 'two-phase optimization' algorithm is used with iter-frame dependency model. While the existing approaches are almost impossible to find the macroblock-unit result for the moving picture coding system due to high computational complexity, the proposed algorithm can drastically reduce the computational loads by the problem partitioning and can obtain the result close to the optimal solution. Because the optimally allocated results can be used as a benchmark for bit allocation methods, the upper performance limit, or a basis for approximation method development, we expect that the proposed algorithm can be very useful for the bit allocation related works.

• Korean Journal of Optics and Photonics
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• v.18 no.2
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• pp.122-129
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• 2007

Generally, many kinds of phase unwrapping algorithm are used to obtain three-dimensional features in digital holography. The Goldstein algorithm is ra epresentative method. which requires small memory capacity and short execution time fer an unwrapping process. However, the Goldstein algorithm has some problems when the dipole residue is located at the boundary. When the opposite residues are located at the boundary and the distance between the opposite residues is longer than the boundary, an incorrect branch cut occurs and results in incorrect calculation. We have modified the Goldstein algorithm to solve the incorrect calculation problem using boundary information. We found that the modified Goldstein algorithm could resolve the Goldstein algorithm's problem.

• Journal of Digital Contents Society
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• v.16 no.5
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• pp.805-813
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• 2015

Many researchers expect the compressive sensing and sparse recovery problem can overcome the limitation of conventional digital techniques. However, these new approaches require to solve the l1 norm optimization problems when it comes to signal reconstruction. In the signal reconstruction process, the transform computation by multiplication of a random matrix and a vector consumes considerable computing power. To address this issue, parallel processing is applied to the optimization problems. In particular, due to huge size of original signal, it is hard to store the random matrix directly in memory, which makes one need to design a procedural approach in handling the random matrix. This paper presents a new parallel algorithm to calculate random partial Haar wavelet transform based on Single Instruction Multiple Threads (SIMT) platform.

• Journal of the Korea Society of Computer and Information
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• v.17 no.12
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• pp.149-158
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• 2012

Proposed is a hybrid randomizing function using two asymptotically optimal randomizing functions: Elias function and Peres function. Randomizing function is an mathematical abstraction of producing a uniform random bits from a source of randomness with bias. It is known that the output rate of Elias function and Peres function approaches to the information-theoretic upper bound. Especially, for each fixed input length, Elias function is optimal. However, its computation is relatively complicated and depends on input lengths. On the contrary, Peres function is defined by a simple recursion. So its computation is much simpler, uniform over the input lengths, and runs on a small footprint. In view of this tradeoff between computational complexity and output efficiency, we propose a hybrid randomizing function that has strengths of the two randomizing functions and analyze it.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.999-1008
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• 2012

Unlike the existing CMOS chip, ISB (Intelligent Silicon Bead) is new concept biochip equipped with optical communication and memory function. It uses the light for power of SoC CMOS and interface with external devices therefore it is possible to miniaturize a chip size and lower the cost. This paper introduces an input protocol and a design of the low power and the low area to transfer the power and the signal through a single optical signal applied from external reader device to bead chip at the same time. It is also verified through simulation and measurement. In addition, low-power PROM is designed for recording and storing ID of a chip and it is successful in obtaining the value of output according to the optical input. Through this study, a new type biochip development can be expected by solving high cost and a limit of miniaturizing a chip area problem of an existing RFID.