• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.377-384
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• 2007

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. In this paper, We proposed a reallocation algorithm for faulty memory part to efficient reallocation with row and column redundant memory. Reallocation information obtained from faulty memory by only every test. Time overhead problem occurs geting reallocation information as every test. To its avoid, one test resulted from reallocation information can save to flash memory. In this paper, reallocation information increases efficiency using flash memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.69-81
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• 2008

The density of Memory has been increased by great challenge for memory technology, so elements of memory become smaller than before and the sensitivity to faults increases. As a result of these changes, memory testing becomes more complex. The number of storage elements is increased per chip, and the cost of test becomes more remarkable as the cost per transistor drops. Proposed design doesn't need to control from outside environment, because it integrates into memory. The proposed scheme supports the various memory testing algorithms. Consequently, the proposed one is more efficient in terms of test cost and test data to be applied. Moreover, we proposed a reallocation algorithm for faulty memory parts. It has an efficient reallocation scheme with row and column redundant memory. Previous reallocation information is obtained from faulty memory every each tests. However proposed scheme avoids to this problem. because onetime test result from reallocation information can save to flash memory. In this paper, a reallocation scheme has been increased efficiency because of using flash memory.

• The Journal of the Korea Contents Association
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• v.8 no.4
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• pp.48-54
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• 2008

This paper analyzes cost tradeoffs between memory usage and computation for window-based operators in data stream environments. It identifies generic operator network constructs, and sets up a cost model for the estimation of the expected memory reduction and the computation overheads when window memory relocations are applied to each operator network construct. This cost model helps to identify the utility of window memory relocations. It also helps to apply window memory relocation to improve a query execution plan to save memory usage. The proposed approach contributes to expand the scope of query processing and optimization in data stream environments. It also provides a basis to develop a cost estimation model for the query optimization using window memory relocations.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.841-843
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• 2005

최근 64비트 CPU의 시장 출시가 활발해지고 있으며, 메모리 모듈 또한 대용화가 이루어지고 있다. 이에 대용량 메모리를 64비트 CPU 플랫폼에서 효과적으로 테스트하는 방법을 개발할 필요성이 대두되고 있다. 본 논문에서는 x86-64 기반 리눅스 2.6.11 커널에서 물리 메모리의 테스트 영역을 확장하는 기법을 제안한다. 제안된 기법에는 응용이나 커널에서 물리 메모리에 대한 직접 접근, 프로그램을 사용자가 원하는 물리 메모리로 배치, 프로그램의 동적 재배치 등의 방법을 통해 테스트 영역을 확장 한다. 현재 64 비트 CPU를 지원하는 OS는 리눅스와 윈도우즈 64비트 에디션 등이 있다. 기존 리눅스 커널을 그대로 사용하였을 때 프로그램 등이 이미 사용 중인 물리 메모리에 대해서는 메모리 테스트를 수행 할 수 없었으나, 각 프로그램들을 물리 메모리에서 재배치하여, 원하는 곳의 메모리를 테스트 할 수 있도록 커널 수정을 통하여 구현하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.73-79
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• 2009

With the advance of VLSI technology, the capacity and density of memories are rapidly growing. In this paper we proposed MRI (Memory built-in self Repair Imagination zone) as reallocation algorithm. All faulty cells of embedded memory are reallocated into the row and column spare memory. This work implements reallocation algorithm and BISR to verify its design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.113-120
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• 2007

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. In this paper we proposed reallocation algorithm. All faulty cell of embedded memory is reallocated into the row and column spare memory. This work implements reallocation algorithm and BISR to verify its design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.328-335
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• 2005

bIn this paper, built-in self-repair(BISR) is proposed for semiconductor memories. BISR is consisted of BIST(Buit-in self-test) and BIRU(Built-In Remapping Uint). BIST circuits are required not oがy to detect the presence of faults but also to specify their locations for repair. The memory rows are virtually divided into row blocks and reconfiguration is performed at the row block level instead of the traditional row level. According to the experimental result, we can verify algorithm for replacement of faulty cell.

• Electronics and Telecommunications Trends
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• v.13 no.2 s.50
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• pp.29-42
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• 1998

이제까지 대부분의 소프트웨어 작성자들은 순차 유지적(sequential consistency) 메모리모델을 기본으로 생각하여 프로그램을 작성하였다. 그러나 이 모델은 쓰기버퍼, 명령어 재배치 등과 같은 하드웨어적인 성능증가뿐 아니가 소프트웨어적인 성능증가기법들을 사용하는 데 많은 제약으로 작용하였다. 따라서 대규모 성능이 우수한 프로그램 실행환경을 채택하고 있다. 이러한 유연한 메모리모델은 분류하기에 따라 매우 다양하지만 일반적으로 process consistency, weak consistency, release consistency 등을 예로 들 수 있다. 본 고에서는 가장 일반적이고 대표적인 메모리 모델인 sequential consistency에 대해 여러 예를 통해 살펴보고, 이제까지 제안되거나 분류된 여러 메모리 모델에 대해 살펴보고 결론을 맺는다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.337-338
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• 2018

본 논문에서는 개발자가 범용 리눅스 운영체제에서 유연하게 시스템의 실시간성 향상을 이뤄낼 수 있도록 자원재배치 모듈을 통한 스케줄링 기법을 제안한다. 제안하는 방법은 범용 리눅스 운영체제 기반이기 때문에 기존의 Cyber-Physical System (CPS)에 쉽게 적용이 가능하며, 실시간성을 필요로 하는 새로운 CPS 프로젝트의 개발 속도 향상시킬 것으로 예상된다. 또한, 실험결과 자원 재배치를 진행한 애플리케이션의 평균 처리율이 20%이상 증가한 것을 알 수 있다. 추후 메모리, I/O장치 등 다양한 자원에 대하여 모니터링을 진행하고 자원을 재배치 할 수 있는 플랫폼으로 확장할 예정이다.

• The KIPS Transactions:PartD
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• v.15D no.1
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• pp.99-106
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• 2008

Recently developed compilers perform some optimizations in order to speed up the execution time of source program. These optimizations require the reordering of the sequence of program statements. This reordering does not give any problems in a single-threaded program. However, the reordering gives some significant errors in a multi-threaded program. State-of-the-art model checkers such as JavaPathfinder do not consider the reordering resulted in the optimization step in a compiler since they just consider a single memory model. In this paper, we develop a new verification tool to verify Java source program based on Java Memory Model. And our tool is capable of handling the reordering in verifying Java programs. As a result, our tool finds an error in the test program which is not revealed with the traditional model checker JavaPathFinder.