• Journal of KIISE:Computing Practices and Letters
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• v.15 no.1
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• pp.1-13
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• 2009

Flash memory is widely used as a storage medium of mobile devices such as MP3 players, cellular phones and digital cameras due to its tiny size, low power consumption and shock resistant characteristics. Currently, there are many studies to replace HDD with flash memory because of its numerous strong points. To use flash memory as a storage medium, FTL(Flash Translation Layer) is required since flash memory has erase-before-write constraints and sizes of read/write unit and erase unit are different from each other. Recently, new type of flash memory called "large block flash memory" is introduced. The large block flash memory has different physical structure and characteristics from previous flash memory. So existing FTLs are not efficiently operated on large block flash memory. In this paper, we propose an efficient FTL for large block flash memory based on FAST(Fully Associative Sector Translation) scheme and page-level mapping on data blocks.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.177-185
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• 2005

NAND-type flash memory is becoming increasingly popular as a large data storage for mobile computing devices. Since flash memory is an order of magnitude more expensive than magnetic disks, data compression can be effectively used in managing flash memory based storage systems. However, compressed data management in NAND-type flash memory is challenging because it supports only page-based I/Os. For example, when the size of compressed data is smaller than the page size. internal fragmentation occurs and this degrades the effectiveness of compression seriously. In this paper, we present an efficient flash compression layer (FCL) for NAND-type flash memory which stores several small compressed pages into one physical page by using a write buffer Based on prototype implementation and simulation studies, we show that the proposed scheme offers the storage of flash memory more than $140\%$ of its original size and expands the write bandwidth significantly.

• Journal of the Korean Institute of Intelligent Systems
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• v.19 no.1
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• pp.54-61
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• 2009

This paper presents a new electromyogram (EMG) pattern recognition method based on the Hierarchical Temporal Memory (HTM) algorithm which is originally devised for image pattern recognition. In the modified HTM algorithm, a simplified two-level structure with spatial pooler, temporal pooler, and supervised mapper is proposed for efficient learning and classification of the EMG signals. To enhance the recognition performance, the category information is utilized not only in the supervised mapper but also in the temporal pooler. The experimental results show that the ten kinds of hand motion are successfully recognized.

• Journal of Korea Multimedia Society
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• v.9 no.2
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• pp.244-254
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• 2006

This paper presents an efficient hybrid technique to compact the trie indexing the huge forward table small enough to be stored into cache for speeding up IP lookup. It combines two techniques, an encoding scheme called bit-map and a controlled-prefix expanding scheme to replace slow memory search with few fast-memory accesses and computations. For compaction, the bit-map represents each index and child pointer with one bit respectively. For example, when one node denotes n bits, the bit-map gives a high compression rate by consumes $2^{n-1}$ bits for $2^n$ index and child link pointers branched out of the node. The controlled-prefix expanding scheme determines the number of address bits represented by all root node of each trie's level. At this time, controlled-prefix scheme use a dynamic programming technique to get a smallest trie memory size with given number of trie's level. This paper proposes standard that can choose suitable trie structure depending on memory size of system and the required IP lookup speed presenting optimal memory size and the lookup speed according to trie level number.

• Journal of KIISE
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• v.44 no.11
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• pp.1130-1137
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• 2017

The multi-leveling technique that stores multiple bits in a single memory cell has significantly improved the density of NAND flash memory along with shrinking processes. However, because of the side effects of the multi-leveling technique, the average write performance of MLC NAND flash memory is degraded more than twice that of SLC NAND flash memory. In this paper, we introduce existing cross-layer optimization techniques proposed to improve the performance of MLC NAND flash-based storages, and propose a new integration technique that overcomes the limitations of existing techniques by exploiting their complementarity. By fully exploiting the performance asymmetry in MLC NAND flash devices at the flash translation layer, the proposed technique can handle many write requests with the performance of SLC NAND flash devices, thus significantly improving the performance of NAND flash-based storages. Experimental results show that the proposed technique improves performance 39% on average over individual techniques.

• Journal of Digital Contents Society
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• v.16 no.4
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• pp.535-543
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• 2015

Recently, NAND flash based storage devices are being used as a storage device in various fields through hiding the limitations of NAND flash memory and maximizing the advantages. In particular, those storage devices contain a software layer called Flash Translation Layer(FTL) to hide the "erase-before-write" characteristics of NAND flash memory. FTL includes the metadata for managing the data requested from host. That metadata is stored in internal memory because metadata is very frequently accessed data for processing the requests from host. Thus, if the power-loss occurs, all data in memory is lost. So metadata management scheme is necessary to store the metadata periodically and to load the metadata in the initialization step. Therefore we proposed the scheme which satisfies the core requirements for metadata management and efficient operation. And we verified the efficiency of proposed scheme by experiments.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.445-458
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• 2007

This article presents a novel infrastructure for large-memory database processing using commodity hardware with operating system support. We exploit inexpensive PCs and a high-speed network capable of Remote Direct Memory Access (RDMA) operations to build a new memory hierarchy between fast volatile memory and slow disk storage. The new memory hierarchy guarantees a reasonable response time, and its storage size enables us to run large-memory database systems with little performance degradation. The proposed architecture has two main components: (1) a remote memory system inside the Linux kernel to manage other computers' memory pages efficiently and (2) a remote memory pager responsible for manipulating remote read/write operations on remote memory pages. We insist that the proposed architecture is practical enough to support the rigorous demands of commercial in-memory database systems by demonstrating the performance of publicly available main-memory databases (e.g., MySQL) on our prototyped system. The experimental results show very interesting results from the TPC-C benchmark.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06a
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• pp.290-292
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• 2012

스마트폰 등의 임베디드 시스템에서는 낸드 플래시 기반 저장장치를 주로 사용한다. 하지만 지금까지의 운영체제의 블록 IO 시스템은 하드 디스크를 대상으로 설계되었기 때문에 낸드 플래시 메모리 기반의 저장장치의 특성을 고려하지 못하였다. 또한, 낮은 성능의 하드디스크에서는 운영체제에서 IO를 처리하는 소프트웨어 계층의 부하가 무시될 수 있었으나, 고성능의 낸드 플래시 메모리에서는 문제가 될 수 있다. 본 논문에서는 스마트 디바이스의 운영체제 중 하나인 안드로이드 플랫폼을 기반으로 IO 요청을 수행하는 소프트웨어 계층별 성능을 측정하였으며, 또한 멀티 프로세스상에서 IO 성능에 어떤 영향을 받는지 관찰했다. 실험 결과 IO 요청의 단위가 작은 경우는 운영체제에서의 부하가 저장장치에서 요청을 처리하는 지연 시간보다 압도적으로 크게 나타났으며, 16KB 단위의 IO 요청에 대해서 전체 지연 시간의 90%를 차지하였다. 또한, 멀티 프로세스 환경에서 IO를 처리하면서 인터럽트를 처리하는 시간이 증가하는 것을 확인했다.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.538-540
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• 2001

클러스터 시스템의 각 노드에 존재하는 메모리들을 효율적으로 관리하기 위하여 네트워크 메모리의 개념이 등장하였으며 빈번하게 디스크를 접근하는 응용분야에서 속도 향상을 위해 사용될 수 있다. 이는 전통적인 메모리 계층(hierarchy) 구조인 메모리와 디스크 사이에 네트워크 메모리를 추가함으로써 얻어진다. 본 논문에서는 웹 서버 클러스터를 대상으로 문서의 접근 유형에 대한 사전의 정보를 요구하지 않고 실제적으로 구현 가능하며 다양한 웹 문서 접근 확률 분포 값에 대하여 항상 우수한 사용자 응답시간을 가지는 메모리 관리 기법을 제안하고 시뮬레이션을 통해 제안된 방식의 우수성을 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.5 s.311
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• pp.1-7
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• 2006

This paper presents experimental instruction-level current consumption model for low power microcontroller ATmega128. The accessibility of instruction for internal memory decides power consumption of the microcontroller as much as 17% of difference between access instruction and non-access instruction. The power consumption for the given program will be increased in the proportional to the ratio of memory access instruction and lower level memory access in the hierarchy. Throughout the current consumption model, the power consumption can be predicted and optimized in the direction of reducing the frequency memory access. Also, the various optimization methods are introduced in terms of software and hardware viewpoints.