• Journal of KIISE:Computer Systems and Theory
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• v.29 no.7
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• pp.422-430
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• 2002

For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Since the maximum number of the LUT's required in the same time determines the size of the chip used in the synthesis, it needs to be minimized, if possible. Many previous work use their own approaches, which are very similar to either scheduling method in high level synthesis or multi-way circuit partitioning method, to solve the problem. In this paper, we propose a method which estimates the lower bound on the number of LUT's without performing any actual synthesis. The estimated lower bounds help to evaluate the results of the previous work. If the estimated lower bound on the number of LUT's exactly matches the number of LUT's of the result from the previous work, the result must be optimal. In contrast, if they do not match, the following two cases are expected : the more exact lower bound may exist, or we might find the new synthesis result better than the result from the previous work. Experimental results show that our lower bound estimation method is very accurate. In almost al] cases experimented, the estimated lower bounds on the number of LUT's exactly match those of the previous synthesis results respectively, implying that the best results from the previous work are optimal as well as our method predicted the exact lower bound for those examples.

• Journal of The Korean Association of Information Education
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• v.9 no.3
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• pp.453-462
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• 2005

Recently, due to technical improvements of storage devices and networks, the amount of data increase rapidly. In addition, it is required to find the knowledge embedded in a data stream as fast as possible. Huge data in a data stream are created continuously and changed fast. Various algorithms for finding frequent itemsets in a data stream are actively proposed. Current researches do not offer appropriate method to find frequent itemsets in which flow of time is reflected but provide only frequent items using total aggregation values. In this paper we proposes a novel algorithm for finding the relative frequent itemsets according to the time in a data stream. We also propose the method to save frequent items and sub-frequent items in order to take limited memory into account and the method to update time variant frequent items. The performance of the proposed method is analyzed through a series of experiments. The proposed method can search both frequent itemsets and relative frequent itemsets only using the action patterns of the students at each time slot. Thus, our method can enhance the effectiveness of learning and make the best plan for individual learning.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.45-52
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• 1994

In recent days low cost, high performance microprocessors have led to construction of medium scale shared memory multiprocessor systems with shared bus. Such multiprocessor systems are heavily influenced by the structures of memory systems and memory systems become more important factor in design space as microprocessors are getting faster. Even though local cache memories are very common for such systems, the latency on access to the shared memory limits throughput and scalability. There have been many researches on the memory structure for multiprocessor systems. In this paper, an asynchronous memory architecture is proposed to utilize the bandwith of system bus effectively as well as to provide flexibility of implementation. The effect of the proposed architecture if shown by simulation. We choose, as our model of the shared bus is HiPi+Bus which is designed by ETRI to meet the requirements of the High-Speed Midrange Computer System. The simulation is done by using Verilog hardware decription language. With this simulation, it is explored that the proposed asynchronous memory architecture keeps the utilization of system bus low enough to provide better throughput and scalibility. The implementation trade-offs are also described in this paper. The asynchronous memory is implemented and tested under the prototype testing environment by using test program. This intensive test has validated the operation of the proposed architecture.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.11
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• pp.63-77
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• 1994

This paper describes the real-time system which, through analyzing a sequence of images, can extract motional information on a moving object and can contol servo equipment to always locate the moving object at the center of an image frame. An image is a vast amount of two-dimensional signal, so it takes a lot of time to analyze the whole quantity of a given image. Especially, the time needed to load pixels from a memory to processor increase exponentially as the size of an image increases. To solve such a problem and track a moving object in real-time, this paper addresses how to selectively search the spatial and time domain. Based on the selective search of spatial and time domain, this paper suggests various types of techniques which are essential in implementing a real-time tracking system. That is, this paper describes how to detect an entrance of a moving object in the field of view of a camera and the direction of the entrance, how to determine the time interval of adjacent images, how to determine nonstationary areas formed by a moving object and calculated velocity and position information of a moving object based on the determined areas, how to control servo equipment to locate the moving object at the center of an image frame, and how to properly adjust time interval(${\Delta}$t) to track an object taking variable speed.

• Journal of KIISE:Databases
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• v.37 no.1
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• pp.1-11
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• 2010

Recently, there has been a growing interest in the processing of continuous queries over multiple data streams. When the arrival rates of tuples exceed the memory capacity of the system, a load shedding technique is used to avoid the system becoming overloaded by dropping some subset of input tuples. In this paper, we propose an effective load shedding algorithm for multi-way windowed joins over multiple data streams. Most previous load shedding algorithms estimate the productivity of each tuple, i.e., the number of join output tuples produced by the tuple, based on its "join attribute value" and drop tuples with the lowest productivity. However, the productivity of a tuple cannot be accurately estimated from its join attribute value when the join attribute values are unique and do not repeat, or the distribution of the join attribute values changes over time. For these cases, we estimate the productivity of a tuple based on its "arrival order" on data streams, rather than its join attribute value. The proposed method can effectively estimate the productivity of a tuple even when the productivity of a tuple cannot be accurately estimated from its join attribute value. Through extensive experiments and analysis, we show that our proposed method outperforms the previous methods in terms of effectiveness and efficiency.

• Journal of KIISE:Information Networking
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• v.35 no.6
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• pp.497-509
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• 2008

Various algorithms and architectures for efficient packet classification have been widely studied. Packet classification algorithms based on a decision tree structure such as HiCuts and HyperCuts are known to be the best by exploiting the geometrical representation of rules in a classifier. However, the algorithms are not practical since they involve complicated heuristics in selecting a dimension of cuts and determining the number of cuts at each node of the decision tree. Moreover, the cutting is not efficient enough since the cutting is based on regular interval which is not related to the actual range that each rule covers. In this paper, we proposed a new efficient packet classification algorithm using a range cutting. The proposed algorithm primarily finds out the ranges that each rule covers in 2-dimensional prefix plane and performs cutting according to the ranges. Hence, the proposed algorithm constructs a very efficient decision tree. The cutting applied to each node of the decision tree is optimal and deterministic not involving the complicated heuristics. Simulation results for rule sets generated using class-bench databases show that the proposed algorithm has better performance in average search speed and consumes up to 3-300 times less memory space compared with previous cutting algorithms.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.9
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• pp.597-604
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• 2016

A parallel algorithm of bi-conjugate gradient method was developed based on CUDA for parallel computation of the incompressible Navier-Stokes equations. The governing equations were discretized using splitting P2P1 finite element method. Asymmetric stenotic flow problem was solved to validate the proposed algorithm, and then the parallel performance of the GPU was examined by measuring the elapsed times. Further, the GPU performance for sparse matrix-vector multiplication was also investigated with a matrix of fluid-structure interaction problem. A kernel was generated to simultaneously compute the inner product of each row of sparse matrix and a vector. In addition, the kernel was optimized to improve the performance by using both parallel reduction and memory coalescing. In the kernel construction, the effect of warp on the parallel performance of the present CUDA was also examined. The present GPU computation was more than 7 times faster than the single CPU by double precision.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.5
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• pp.245-256
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• 2002

Shadows are important elements in producing a realistic image. Generation of exact shapes and positions of shadows is essential in rendering since it provides users with visual cues on the scene. It is also very important to be able to create soft shadows resulted from area light sources since they increase the visual realism drastically. In spite of their importance. the existing shadow generation algorithms still have some problems in producing realistic shadows in real-time. While image-based rendering techniques can often be effective1y applied to real-time shadow generation, such techniques usually demand so large memory space for storing preprocessed shadow maps. An effective compression method can help in reducing memory requirement, only at the additional decoding costs. In this paper, we propose a new image-barred shadow generation method based on image warping. With this method, it is possible to generate realistic shadows using only small sizes of pre-generated shadow maps, and is easy to extend to soft shadow generation. Our method will be efficiently used for generating realistic scenes in many real-time applications such as 3D games and virtual reality systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.7C
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• pp.691-699
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• 2006

Despite of the in-depth effort to cantrol the variability in IP networks, quality of service (QoS) is still not guaranteed in the IP networks. Thus, it is necessary to deal with the audible artifacts caused by packet lasses. To overcame the packet loss problem, most speech coding standard have their own embedded packet loss concealment (PLC) algorithms which adapt extrapolation methods utilizing the dependency on adjacent frames. Since many low bit rate CELP coders use predictive schemes for increasing coding efficiency, however, error propagation occurs even if single packet is lost. In this paper, we propose an efficient PLC algorithm with consideration about the speech characteristics of lost frames. To design an efficient PLC algorithm, we perform several experiments on investigating the error propagation effect of lost frames of a predictive coder. And then, we summarize the impact of packet loss to the speech characteristics and analyze the importance of the encoded parameters depending on each speech classes. From the result of the experiments, we propose a new PLC algorithm that mainly focuses on reducing the error propagation time. Experimental results show that the performance is much higher than conventional extrapolation methods over various frame erasure rate (FER) conditions. Especially the difference is remarkable in high FER condition.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.8-15
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• 2009

Side-channel attacks including the differential power analysis attack are often more powerful than classical cryptanalysis and have to be seriously considered by cryptographic algorithm's implementers. Various countermeasures have been proposed against such attacks. In this paper, we deal with the masking method, which is known to be a very effective countermeasure against the differential power analysis attack and propose new gate-level conversion methods between Boolean and arithmetic masks. The new methods require only 6n-5 XOR and 2n-2 AND gates with 3n-2 gate delay for converting n-bit masks. The basic idea of the proposed methods is that the carry and the sum bits in the ripple adder are manipulated in a way that the adversary cannot detect the relation between these bits and the original raw data. Since the proposed methods use only bitwise operations, they are especially useful for DPA-securely implementing cryptographic algorithms in hardware which use both Boolean and arithmetic operations. For example, we applied them to securely implement the block encryption algorithm SEED in hardware and present its detailed implementation result.