• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.159-160
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• 2012

지난 30년 동안 플래시 메모리의 주류 역할을 하였던 부유 게이트 플래시 메모리는 40 nm 기술 노드 이하에서 셀간 간섭, 터널 산화막의 누설전류 등에 의한 오동작으로 기술적 한계를 맞게 되었다. 또한 기존의 비휘발성 메모리는 동작 시 높은 전압을 요구하므로 전력소비 측면에서도 취약한 단점이 있다. 그러나 이러한 문제점들을 기존의 Si기반의 소자기술이 아닌 새로운 재료나 공정을 통해서 해결하려는 연구가 최근 활발하게 진행되고 있다. 특히, 플래시 메모리의 중요한 구성요소의 하나인 터널 산화막은 메모리 소자의 크기가 줄어듦에 따라서 SiO2단층 구조로서는 7 nm 이하에서 stress induced leakage current (SILC), 직접 터널링 전류의 증가와 같은 많은 문제점들이 발생한다. 한편, 기존의 부유 게이트 타입의 메모리를 대신할 것으로 기대되는 전하 포획형 메모리는 쓰기/지우기 속도를 향상시킬 수 있으며 소자의 축소화에도 셀간 간섭이 일어나지 않으므로 부유 게이트 플래시 메모리를 대체할 수 있는 기술로 주목받고 있다. 특히, TBM (tunnel barrier engineered memory) 소자는 유전율이 큰 절연막을 적층하여 전계에 대한 터널 산화막의 민감도를 증가시키고, 적층된 물리적 두께의 증가에 의해 메모리의 데이터 유지 특성을 크게 개선시킬 수 있는 기술로 관심이 증가하고 있다. 본 연구에서는 Si3N4/Ta2O5를 적층시킨 staggered구조의 tunnel barrier를 제안하였고, Si기판 위에 tunnel layer로 Si3N4를 Low Pressure Chemical Vapor Deposition (LPCVD) 방법과 Ta2O5를 RF Sputtering 방법으로 각각 3/3 nm 증착한 후 e-beam evaporation을 이용하여 게이트 전극으로 Al을 150 nm 증착하여 MIS- capacitor구조의 메모리 소자를 제작하여 동작 특성을 평가하였다. 또한, Si3N4/Ta2O5 staggered tunnel barrier 형성 후의 후속 열처리에 따른 전기적 특성의 개선효과를 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.3
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• pp.20-33
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• 2002

As dual port RAMs are widely used in the various applications, the need for an efficient algorithm to diagnose faults in dual port RAMs is increased. In this paper we propose an efficient algorithm that can diagnose all kinds of faults in dual port RAMs. In addition, the new algorithm can distinguish various fault models and locate the position related to each fault. Using the new algorithm, fault diagnosis for dual port RAMs can be performed efficiently and the performance evaluation with previous approaches proves the efficiency of the new algorithm.

• Journal of the Korea Computer Industry Society
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• v.2 no.2
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• pp.211-218
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• 2001

In this paper, we propose the structure of utilizing the memory map, which is using not conventional DRAM but SDRAM, for the hardware implementation of frame memory interface module to the video encoder. As reducing the size of memory map and interface buffer within the same bus, the hardware complexity is improved and the hardware size is minimized as simplifying the interface logic. The conventional system is wasted access time, because of accessing randomly stored data in order to store and output the memories in macro-block unit. therefore the method, which is proposed in this paper, can be effectively reducing the access time of memory, because of the data is stored and processed by line unit.

• KIISE Transactions on Computing Practices
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• v.23 no.3
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• pp.165-170
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• 2017

Many studies have utilized GPGPU (General-Purpose Graphic Processing Unit) and its high computing power to compute complex tasks. The characteristics of GPGPU programs necessitate the operations of memory copy between the host and device. A high latency period can affect the performance of the program. Thus, it is required to significantly improve the performance of GPGPU programs by optimizations. By executing multiple GPGPU programs simultaneously, the latency hiding effect of memory copy is achieved by overlapping the memory copy and computing operations in GPGPU. This paper presents the results of analyzing the latency hiding effect for memory copy operations. Furthermore, we propose a performance anticipation model and an algorithm for the limitations of using pinned memory, and show that the use of the proposed algorithm results in a 41% performance increase.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.44-52
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• 2002

Since memory technology has been developed fast, test complexity and test time have been increased simultaneously. In practice, March algorithms are used widely for detecting various faults. However, March algorithms cannot detect NPSFs(Neighborhood Pattern Sensitive Faults) which must be considered for DRAMs. This paper proposes an effective algorithm for high fault coverage by modifying the conventional March algorithms.

• Journal of IKEEE
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• v.21 no.4
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• pp.353-357
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• 2017

In order to maintain numerous server systems used in enterprise and data center environments, the most important thing is to prevent the occurrence of UE (Uncorrectable Error) of each server system. With the recent development of cloud services, more memory modules are being used than ever before, while the operating frequency of server systems has increased and the process of developing memory has continued to shrink, making it more likely to fail. In these environments, there is a way to repair memory defects directly in the server system, but there is no currently available guideline to use it effectively. In this paper, we propose a method to effectively prevent memory failure in a server system based on the observation and analysis of memory failure phenomenon in existing system.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.2
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• pp.275-282
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• 2015

Since a NAND-flash memory is able to keep data during electricity-off and has small cost to store data per bytes, it is widely used on hand-held devices. It is necessary to use an index in order to process mass data effectively on the flash memory. However, since the flash memory requires high cost for a write operation and does not support an overwrite operation, it is possible to reduce the performance of the index when the disk based index is exploited. In this paper, we implement the fixed grid file index and evaluate the performance of the index on various conditions. To do this, we measure the average processing time by the ratio of query operations and update operations. We also the compare the processing times of the flash memory with those of the magnetic disk.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.9
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• pp.461-468
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• 2001

Though shared virtual memory (SVM) system promise low cost solutions for high performance computing they suffer from long memory latencies. These latencies are usually caused by repetitive invalidations on shared data. Since shared data are accessed through synchronization and the patterns by which threads synchronizes are repetitive, a prefetching scheme bases on such repetitiveness would reduce memory latencies. Based on this observation, we propose a prefetching technique which predicts future access behavior by analyzing access history per synchronization variable. Our technique was evaluated on an 8-node SVM system using the SPLASH-2 benchmark. The results show the our technique could achieve 34%~45% reduction in memory access latencies.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.05a
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• pp.96-99
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• 2021

NVRAM(Non-volatile RAM)이란 전원을 공급하지 않아도 데이터를 유지할 수 있는 RAM 이다. 비휘발성 메모리이기 때문에 Flash 와 동일한 기능을 제공할 수 있다. 또한 Flash 에 비해 저전력으로 동작하고, 읽고 쓰는 동작도 더 빠르며 내구성까지 뛰어나다. 즉, NVRAM 은 리소스가 제한적인 사물인터넷(IoT) 장치에서 Flash 를 대신하여 전력소모 및 지연시간 측면에서 효과적으로 사용될 수 있는 메모리이다. IoT 장치는 일반적으로 배터리와 같은 독립전원 장치로 작동하거나, 최근에는 에너지 하베스터를 활용한 간헐적 컴퓨팅 방식도 활용되고 있다. 간헐적 컴퓨팅 방식에서는 전원이 꺼졌을 때도 프로그램의 상태를 유지하기 위해 비휘발성 메모리에 백업동작이 필수적이다. 그러므로 백업을 위한 메모리를 Flash 가 아닌 NVRAM 으로 대체하게 되면 효율적이고, 상대적으로 백업 및 복구에 의한 비휘발성 메모리에 접근이 많은 간헐적 컴퓨팅에서는 더 큰 효율을 볼 수 있다. 하지만 현재 NVRAM 이 내장된 개발보드가 제한적이고, NVRAM 을 외부 모듈로서 사용하기 위해 SPI 또는 I2C 통신을 사용해야 한다. 그 외에도 동시에 공유 메모리에 접근하는 등의 문제를 막아야 한다. 이러한 문제를 막고, NVRAM 을 편리하게 사용할 수 있도록 추상화 계층을 만들어 NVRAM 테스팅 환경을 제공하여 해당 분야의 연구개발을 가속화할 수 있을 것으로 기대된다. 본 논문에서는 NVRAM 의 한 종류인 FRAM 을 사용하여 추상화 계층을 구현하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.341-344
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• 2001

We investigate the electronic structure of perovskite PbTiO$_3$ and the microscopic origin of the ferroelectric lattice instability through first-principles pseudopotential calculations. We examine pseudo Jahn-Teller effect to discuss the lattice instability. The JT effect is caused by the hybridization of the p-orbitals of O atoms and d-orbital of Ti atom. We find the JT effect is most significant at Brillouin zone renter.