• Proceedings of the Korea Information Processing Society Conference
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• 2005.11a
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• pp.155-158
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• 2005

본 논문에서는 MPEG 의 멀티미디어 응용 표준인 MAF(Multimedia Application Format)를 기반으로, 효율적인 비디오 콘텐츠의 검색 및 활용을 위한 통합 미디어 구조, 즉 비디오 MAF 를 제안한다. 제안하는 비디오 MAF 는 ISO 미디어 포맷을 기반으로 하고 단일의 비주얼 스트림과 다중 음성을 지원하기 위한 다수의 오디오 스트림, 내용기반의 정보를 포함하는 메타데이터, 그리고 비디오 콘텐츠의 대표 이미지를 동시에 포함하는 구조이다. 제안하는 파일포맷의 유용성을 검증하기 위해 비디오 MAF 로 생성 및 해석할 수 있는 부호기(encoder)와 복호기(decoder)를 설계하고 구현하여, 통합 미디어에 내재된 메타데이터를 이용한 효율적인 검색과 멀티트랙의 오디오 스트림을 활용한 다중 음성에 대한 지원이 가능함을 확인하였다. 또한 내재된 대표이미지는 비디오 콘텐츠에 대한 브라우징이 효과적으로 활용됨을 확인하였다.

• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.61-68
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• 2008

In this paper, we propose the VLSI design of Multi-Format Video Decoder (MFD) to support video codec standards such as MPEG-2, MPEG-4, H.264 and VC-1. The target of the proposed MFD is the Full HD (High Definition) video processing needed for the high-end D-TV SoC (System-on-Chip). The size of the design is reduced by sharing the common large-size resources such as the RISC processor and the on-chip memory among the different codecs. In addition, a detachable architecture is introduced in order to easily add or remove the codecs. The detachable architecture preserves the stability of the previously designed and verified codecs. The size of the design is about 2.4 M gates and the operating clock frequency is 225MHz in the Samsung 65nm process. The proposed MFD supports more than Full-HD (1080p@30fps) video decoding, and the largest number of video codec standards known so far.

• Journal of Broadcast Engineering
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• v.20 no.6
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• pp.963-966
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• 2015

This paper introduces a programmable multi-format video decoder(MFD) to support HEVC(High Efficiency Video Coding) standard and for other video coding standards. The goal of the proposed MFD is the high-end FHD(Full High Definition) video decoder needed for a DTV(Digital Tele-Vision) SoC(System on Chip). The proposed platform consists of a hybrid architecture that is comprised of reconfigurable processors and flexible hardware accelerators to support the massive computational load and various kinds of video coding standards. The experimental results show that the proposed architecture is operating at a 300MHz clock that is capable of decoding HEVC bit-stream of FHD 30 frames per second.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.182-185
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• 2019

This paper analyzes performances of modules in implementing a programmable multi-format video decoder. The goal of the proposed platform is the high-end Full High Definition (FHD) video decoder. The proposed multi-format video decoder consists of a reconfigurable processor, dedicated bit-stream co-processor, memory controller, cache for motion compensation, and flexible hardware accelerators. The experiments suggest performance baseline of modules for the proposed architecture operating at 300 MHz clock with capability of decoding HEVC bit-streams of FHD 30 frames per second.