• Journal of the Korea Convergence Society
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• v.8 no.5
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• pp.161-167
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• 2017

We have fabricated and characterized $32{\times}32$ photonic quantum ring (PQR) laser arrays uniformly operable with $0.98{\mu}A$ per ring at room temperature. The typical threshold current, threshold current density, and threshold voltage are 20 mA, $0.068A/cm^2$, and 1.38 V. The top surface emitting PQR array contains GaAs multiquantum well active regions and exhibits uniform characteristics for a chip of $1.65{\times}1.65mm^2$. The peak power wavelength is $858.8{\pm}0.35nm$, the relative intensity is $0.3{\pm}0.2$, and the linewidth is $0.2{\pm}0.07nm$. We also report the wavelength division multiplexing system experiment using angle-dependent blue shift characteristics of this laser array. This photonic quantum ring laser has angle-dependent multiple-wavelength radial emission characteristics over about 10 nm tuning range generated from array devices. The array exhibits a free space detection as far as 6 m with a function of the distance.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.592-607
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• 2006

This paper proposes a technique to select processors and hardware IPs and to map the tasks into the selected processing elements, aming to achieve high performance with minimal system cost when multitask applications with real-time constraints are run on a multicore SoC. Such technique is called to 'Hardware-Software Cosynthesis Technique'. A cosynthesis technique was already presented in our early work [1] where we divide the complex cosynthesis problem into three subproblems and conquer each subproblem separately: selection of appropriate processing components, mapping and scheduling of function blocks to the selected processing component, and schedulability analysis. Despite good features, our previous technique has a serious limitation that a task monopolizes the entire system resource to get the minimum schedule length. But in general we may obtain higher performance in multitask multicore system if independent multiple tasks are running concurrently on different processor cores. In this paper, we present two mapping techniques, task mapping avoidance technique(TMA) and task mapping pinning technique(TMP), which are applicable for general cases with diverse operating policies in a multicore environment. We could obtain significant performance improvement for a multimedia real-time application, multi-channel Digital Video Recorder system and for randomly generated multitask graphs obtained from the related works.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.1
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• pp.219-227
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• 2017

Current military command information system uses electronic equipment a lot on which semiconductor chip is attached. It seems its' importance will increase more with latest information communication technology developing. Electronic equipment which uses electricity contains regular tolerance to high output electric signal. And EMC specification is the standardized of this electronic equipment's tolerance. On the other hand, the Institute of Atomic Energy Research has ever declared that high output electromagnetic pulse(EMP) will be broken out within the radius of 170Km when 10kt nuclear explosion occurs at an altitude of 40Km above Seoul. Then, the region suffer from the damage of most electronic equipments. Therefore, the norm to protect the influences in that case is defined by EMP protection specification. Most common electronic equipments meet the EMC norm, but there is no way to check whether they meet the EMP norm or not. That is because it is difficult to check whether they meet EMP protection norm and is on the matter of cost. Except inevitable cases, there is no review of checking whether they meet the norm or not. Considering the above, in this research, we speculate about the measures to improve military EMP protection ability by analyzing the EMC-EMP correlation and checking the EMP protection ability of general electronic equipment through the analysis.

• Journal of the Korea Society of Computer and Information
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• v.16 no.7
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• pp.1-11
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• 2011

Many researchers have studied on the methods to improve the processor performance. However, high integrated semiconductor technology for improving the processor performance causes many problems such as battery life, high power density, hotspot, etc. Especially, as hotspot has critical impact on the reliability of chip, thermal problems should be considered together with performance and power consumption when designing high-performance processors. To alleviate the thermal problems of processors, there have been various researches. In the past, mechanical cooling methods have been used to control the temperature of processors. However, up-to-date microprocessors causes severe thermal problems, resulting in increased cooling cost. Therefore, recent studies have focused on architecture-level thermal-aware design techniques than mechanical cooling methods. Even though architecture-level thermal-aware design techniques are efficient for reducing the temperature of processors, they cause performance degradation inevitably. Therefore, if the mechanical cooling methods can manage the thermal problems of processors efficiently, the performance can be improved by reducing the performance degradation due to architecture-level thermal-aware design techniques such as dynamic thermal management. In this paper, we analyze the cooling efficiency of high-performance multicore processors according to mechanical cooling methods. According to our experiments using air cooler and liquid cooler, the liquid cooler consumes more power than the air cooler whereas it reduces the temperature more efficiently. Especially, the cost for reducing $1^{\circ}C$ is varied by the environments. Therefore, if the mechanical cooling methods can be used appropriately, the temperature of high-performance processors can be managed more efficiently.