• Journal of Korea Multimedia Society
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• v.15 no.1
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• pp.115-130
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• 2012

These days, most of safety-critical systems, which are systems those failures or malfunction may result in death or serious injury to people, or loss or severe damage to social systems, or environmental harm, are being built of embedded software or loaded controlling software systems on computers, electrical and electronic components or devices. There are a lot kind of fault analysis methods to evaluate safety of the safety-critical systems equipped computers, electrical and electronic components or devices with software. However, the only assessment method to evaluate software safety of a safety-critical system is not enough to analysis properly on account of the various types and characteristic of software systems by progress of information technology. Therefore, this paper proposes the integrated evaluation method and carries out a case study for the software safety of safety-critical system which embedded or loaded software sizes are small and control response times are not sensitive by use of two security analysis methods which are Fault Tree Analysis (FTA) and Fault Modes and Effect Analysis (FMEA) for ubiquitous healthcare system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.35-44
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• 2005

SoC(systnn-on-a-chip) requires high bandwidth system bus for performing multiple functions. Performance of the system is affected by bandwidth of the system bus. In this paper, for efficient management of the bus resource on a SoC platform, we present a latency model of the shared bus organized by multiple layers. Using the latency model, we can analyze latencies of the shared bus on a SoC. Moreover we evaluate a throughput of the bus and compare with needed throughput of the SoC platform including IPs such as MPEG or USB 2.0. And we can use the results as a criteria to find out an optimal bus architecture for the specific SoC design. For verifying accuracy of the proposed model, we compared the latencies with the simulation result from MaxSim tools. As the result of simulation, the accuracy of the IS model for a single layer and multiple layer are over $96\%\;and\;85\%$ respectively.

• Journal of Korea Multimedia Society
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• v.8 no.3
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• pp.362-371
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• 2005

This paper presents a digital video broadcasting - terrestrial (DVB-T) receiver system based on the orthogonal frequency division multiplexing (OFDM) modulation method, which has exhibited a good reception performance even with obstacles and a mobile reception. As such, an improved OFDM receiver is developed for a DVB-T system that also considers function expansion for further development. After manufacturing the DVB-T receiver system, the performance of the proposed system is compared with three other hardware systems, all of which are end products. The experimental results confirm the performance using the measured minimum required carrier-to-noise ratio and threshold of visibility signal for each system. In addition, a graphic user interface (GUI) and electronic program guide (EPG) are developed for the digital television user.

• Journal of Korea Multimedia Society
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• v.10 no.1
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• pp.49-57
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• 2007

Recently, CMOS RF integration has been widely explored in the wireless communication area to save cost, power, and chip area. The direct conversion architecture, rather than a more conventional super-het-erodyne, has been an attractive choice for single-chip integration because of its many advantages. However, the direct conversion architecture has several fundamental problems to solve in achieving performance comparable to a super-heterodyne counterpart. In this paper, we describe a programmable filter for mobile communication terminals using a direct conversion architecture. The proposed filter can be implemented with the active-RC filter and programmed to meet the requirements of different communication standards, including GSM, DECT and WCDMA. The filter can be tuned to select a detail frequency by changing the gate voltage of the MOS resistors. The gain of the proposed architecture can be programmed from 27dB to 72dB using the filter gain and VGA in 3dB steps.

• Journal of Korea Multimedia Society
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• v.17 no.1
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• pp.52-59
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• 2014

These days, smart card management system(SCMS) have been broadly used for security conformability, efficiency of issuance management, key management and expert management in the smart card market. SCMS is composed of card management, issuance management, key management, application management, and issuers management systems. SCMS enables card issuers from banks, credit card companies, and telecommunications companies to provide these cards to card users. And then SCMS enables card users to download new programs to chips for use of these cards successively and provide related smart card data in safety and efficiency. In this paper, we propose a framework for security assessment and an efficient method for security improvement through fault analysis which is more effective.

• Journal of Korea Multimedia Society
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• v.12 no.2
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• pp.200-208
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• 2009

JBIG2, as the next generation standard for binary image compression, must be designed in hardware modules for the JBIG2 FAX to be implemented in an embedded equipment. This paper proposes a hardware module of the high-speed Huffman coder for JBIG2. The Huffman coder of JBIG2 uses selectively 15 Huffman tables. As the Huffman coder is designed to use minimal data and have an efficient memory usage, high speed processing is possible. The designed Huffman coder is ported to Virtex-4 FPGA and co-operating with a software modules on the embedded development board using Microblaze core. The designed IP was successfully verified using the simulation function test and hardware-software co-operating test. Experimental results shows the processing time is 10 times faster than that of software only on embedded system, because of hardware design using an efficient memory usage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.79-84
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• 2006

This paper proposed a novel H.264 deblocking filter for low-power mobile multimedia SoCs. In H.264 deblocking filter, filtering can be skipped on some pixels when pixel value differences satisfy some specific conditions. Furthermore, whole filtering can be skipped when quantization parameter is less than 16. Based on these features, power consumption can be significantly reduced by shutting down deblocking filter partially or as a whole. The proposed deblocking filter can shut down partial or whole blocks with simple control circuits. Common hardware performs both horizontal filtering and vertical filtering. It was implemented in silicon chip using $0.35{\mu}m$ standard cell library technology. The gate count is about 20,000 gates. The maximum operation frequency is 108MHz. The maximum throughput is 30 frame/s with CCIR601 image format.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.78-84
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• 2000

The Viterbi decoders can be classified into serial Viterbi decoders and parallel Viterbi decoders. Parallel Viterbi decoders can handle higher data rates than serial Viterbl decoders. This paper designs and implements a fully parallel Viterbi decoder for high speed multimedia communications. For high speed operations, the ACS (Add-Compare-Select) module consisting of 64 PEs (Processing Elements) can compute one stage in a clock. In addition, the systolic away structure with 32 pipeline stages is developed for the TB (traceback) module. The implemented Viterbi decoder can support code rates 1/2, 2/3, 3/4, 5/6 and 7/8 using punctured codes. We have developed Verilog HDL models and performed logic synthesis. The 0.6 ${\mu}{\textrm}{m}$ SAMSUNG KG75000 SOG cell library has been used. The implemented Viterbi decoder has about 100,400 gates, and is running at 70 MHz in the worst case simulation.

• Information and Communications Magazine
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• v.23 no.8
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• pp.35-42
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• 2006

최근 광대역 서비스에 대한 소비자들의 욕구가 차츰 증가하고 있고 대상콘텐츠도 데이터와 음성 및 비디오까지 포함된 멀티미디어 서비스로 변화함에 따라, 통신서비스 제공업체들은 이에 대한 해결책을 찾는 것이 지상과제가 되었다. xDSL, 케이블 모뎀, 광랜 등 엑세스 네트워크가 잘 발달되어 있는 국내에서도 멀티미디어 서비스의 최종 수신 장치가 될 TV, PC, 오디오 기기 및 전화기 등에까지 네트워크를 연결하기 위해서는 댁내에서 또 다른 홈 네트워크를 구성해야 하는 상황이다. 이러한 홈 네트워크를 가능하게 하는 기술로는 홈 RF, 무선랜, 블루투스 등 무선 홈 네트워크 기술과 IEEE1394, 이더넷, 홈 PNA, 전력선통신과 같은 유선 홈 네트워크 기술로 나눌 수 있다. 무선 홈 네트워르 기술의 경우, 댁내에서의 반사와 감쇄 등의 영향에 의한 음영지역이 존재하는 단점이 있고 또 RF단을 구현해야 하므로 시스템 가격이 올라가게 된다. IEEE1394, 이더넷, 홈 PNA 같은 유선 홈 네트워크기술의 경우에는 댁내 통신을 위해 새로운 선을 포설해야 하는데 이를 위해서는 막대한 시설 투자비가 들어가게 된다. 이 막대한 투자비는 홈 네트워크 구축에 많은 시간이 걸리게 하는 요인이 될 뿐만 아니라, 일반 사용자들이 서비스를 이용하기에는 가격적으로 부담스럽게 된다. 전력선통신 (PLC: Power Line Communication) 은 전기를 공급하는 전력선에 흐르고 있는 상용주파수 50/60Hz의 저주파 전력신호에 고주파 신호를 활용하여 데이터를 실어 나르는 통신기술이다. 집안 곳곳 이미 포설되어 있는 전력선이 이미 하나의 네트워크를 구성하고 있기 때문에 번거롭고 값비싼 추가 배선작업 없이 바로 네트워킹이 가능하다. 이와 같은 이유로 고속 PLC는 설치 용이성, 접근성, 속도 및 비용부분 등에서 경쟁기술에 비하여 여러 장점을 가지고 있다. 젤라인은 국내 전력선통신 표준을 만족하는 24Mbps 고속 전력선통신 칩을 기반으로 다양한 전력선 채널환경 하에서 최적의 통신을 보장하는 전력선 통신시스템을 제공하고 있으며, 이를 소개하고자 한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.65-72
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• 2005

We can integrate more IP blocks on a silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processors. However, most of existing SoC buses have bottleneck in on-chip communication because of shared bus architectures, which result in the performance degradation of systems. In most cases, the performance of a multi-processor system is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of the processors. We propose an efficient SoC Network Architecture(SNA) using crossbar routers which provide a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels for multi-masters. According to the proposed architecture, we design a model system for the SNA. The proposed architecture has a better efficiency by $40\%$ than the AMBA AHB according to a simulation result.