• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.345-348
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• 2013

This paper provides a method for compression and transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively.

• Journal of Korea Multimedia Society
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• v.9 no.5
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• pp.542-553
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• 2006

Because Y and C signals in a composite video signal are piled one on another in the same frequency, it is impossible to separate them completely. Therefore, it is necessary to develop efficient separation technique in order to minimize degradation of video quality. In this paper, we propose wavelet-based 3D comb filter algorithm and architecture for separating Y and C signals from a composite video signal. The proposed algorithm uses wavelet transform and thresholding of compared lines for acquiring the maximum video quality. Simulation results show that the proposed algorithm has better image quality and better PSNR than previous algorithms. For real application of the proposed algorithm, we developed a hardware architecture and the architecture was implemented by using VHDL. Finally, a VLSI layout of the proposed architecture was generated by using 0.25 micrometer CMOS process.

• Journal of KIISE:Computing Practices and Letters
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• v.9 no.1
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• pp.13-24
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• 2003

MPEG-4 is a standard for multimedia applications and provides a set of technologies to satisfy the needs of authors, service providers and end users alike. In this paper, we suggest a Real-time Multiple Circular Buffer (M4RM Buffer) model, which is suitable for streaming these MPEG-4 contents efficiently. M4RM buffer generates each structure of the buffer, which matches well with each object composing an MPEG-4 content, according to the transferred information, and manipulates multiple read/write operations only by its reference. It divides the decoder buffer and the composition buffer, which are described in the standard, by the unit of frame allocated to minimize the range of access. This buffer unit of a frame is allocated according to the object description. Also, it processes the objects synchronization within the buffer and provides APIs for an efficient buffer management to process the real-time user events. Based on the performance evaluation, we show that M4RM buffer model decreases the waiting time in a buffer frame, and so allows the real-time streaming of an MPEG-4 content using the smaller size of the memory block than IM1-2D and Window Media Player.

• Journal of IKEEE
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• v.9 no.2 s.17
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• pp.170-178
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• 2005

The video data corrupted by the transmission error due to packet loss induce error propagation in decoded video data, and cause poor video quality. To remedy these corrupted video data, there have been introduced two types of error concealment techniques: spatial or temporal error concealment algorithm. Computational overhead by using spatial error concealment algorithm is a serious disadvantage in mobile video data streaming environment. In this paper, we propose hybrid type error concealment technique recovering video quality of mobile device using MPEG-4 video streaming on error-prone wireless network. Our algorithm is implemented in MPEG-4 decoder. The algorithm adopts Intel Wireless MMX technology to provide high performance of portable embedded multimedia mobile device. It is proven that the proposed algorithm shows expected performance for a mobile streaming system(PDA) on IP channels. Our approach showed better processing speed and better video quality comparing with traditional error concealment algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.439-446
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• 2011

In this paper, we proposed and implemented a dedicated hardware for Huffman coding which is a method of entropy coding to use compressing multimedia data with video coding. The proposed Huffman codec consists Huffman encoder and decoder. The Huffman encoder converts symbols to Huffman codes using look-up table. The Huffman code which has a variable length is packetized to a data format with 32 bits in data packeting block and then sequentially output in unit of a frame. The Huffman decoder converts serial bitstream to original symbols without buffering using FSM(finite state machine) which has a tree structure. The proposed hardware has a flexible operational property to program encoding and decoding hardware, so it can operate various Huffman coding. The implemented hardware was implemented in Cyclone III FPGA of Altera Inc., and it uses 3725 LUTs in the operational frequency of 365MHz

• The Journal of the Acoustical Society of Korea
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• v.23 no.8
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• pp.554-561
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• 2004

As the technologies of semiconductor and multimedia communication have been improved. the high-quality video and the multi-channel audio have been highlighted. MPEG Audio Layer 3 decoder has been implemented as a Processor using a standard. Since the synthesis filter of MPEG-1 Audio Layer 3 decoder requires the most outstanding operation in the entire decoder. the synthesis filter that can reduce the amount of operation is needed for the design of the high-speed processor. Therefore, in this paper, the synthesis filter. the most important part of MPEG Audio, is materialized in FPGA using the method of DAULT (distributed arithemetic look-up table). For the design of high-speed synthesis filter, the DAULT method is used instead of a multiplier and a Pipeline structure is used. The Performance improvement by 30% is obtained by additionally making the result of multiplication of data with cosine function into the table. All hardware design of this Paper are described using VHDL (VHIC Hardware Description Language) Active-HDL 6.1 of ALDEC is used for VHDL simulation and Synplify Pro 7.2V is used for Model-sim and synthesis. The corresponding library is materialized by XC4013E and XC4020EX. XC4052XL of XILINX and XACT M1.4 is used for P&R tool. The materialized processor operates from 20MHz to 70MHz.