• Journal of the Korea Society of Computer and Information
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• v.17 no.8
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• pp.11-19
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• 2012

In this paper, we propose a power-efficient scheduling scheme for lightly loaded multicore processors which contain more processing cores than running tasks. The proposed scheme activates a portion of available cores and inactivates the other unused cores in order to save power consumption. The tasks are assigned to the activated cores based on a heuristic mechanism for fast task assignment. Each activated core executes its assigned tasks with the optimal clock frequency which minimizes the power consumption of the tasks while meeting their deadlines. Evaluation shows that the proposed scheme saves up to 78% power consumption of the previous method which activates as many processing cores as possible for the execution of the given tasks.

• Proceedings of the Korean Society of Computer Information Conference
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• 2017.07a
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• pp.1-2
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• 2017

본 논문에서는 지휘무장통제체계(이하 CFCS) 소프트웨어의 성능 향상 기법으로 고성능 컴퓨팅(이하 HPC) 시스템 활용 기법을 제안한다. 이 기법으로 본 논문에서는 HPC 분야인 멀티코어 프로세서를 활용하는 방법을 제안한다. 복잡한 반복연산을 하는 작업이 많은 CFCS의 특정 SW모듈에 대해 멀티코어 프로세싱 아키텍처를 이용한 병렬처리를 적용하여 기존 순차처리 대비 작업실행시간을 단축함으로써 작업 응답시간을 상당히 줄일 수 있다. 본 논문에서는 CFCS 시험 환경의 일부 특정 SW모듈 상에서 기존의 순차처리 방식으로 수행한 연산 결과와 다중 처리 프로그래밍 API인 OpenMP를 적용하여 수행한 연산 결과를 비교하여 CFCS에서의 멀티코어 프로세싱이 체계 전반의 성능 향상 면에서 효율적으로 사용될 수 있음을 보인다.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.6
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• pp.177-184
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• 2015

This paper proposes a minimum-power scheduling scheme of real-time parallel tasks while meeting deadlines of the real-time tasks on DVFS-enabled multicore processors. The proposed scheme first finds a floating number of processing cores to each task so that the computation load of all processing cores would be equalized. Next the scheme translates the found floating number of cores into a natural number of cores while maintaining the computation load of all cores unchanged, and allocates the translated natural number of cores to the execution of each task. The scheme is designed to minimize the power consumption of the frequency-sharing multicore processor operating with the same processing speed at an instant time. Evaluation shows that the scheme saves up to 38% power consumption of the previous method.

• Journal of Platform Technology
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• v.10 no.2
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• pp.3-9
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• 2022

In this paper, to maximize the performance of the scatter communication in multi-core and many-core processors, a technique that considers the communication situation of the processing node is applied to a multi-core processor composed of 32 processing nodes. Since the existing scatter algorithm cannot recognize the communication conditions of the processing nodes, communication is generally performed according to an initially set transmission order. In this case, scatter communication starts only after the communication currently being performed by all processing nodes inside the processor is finished. The scatter communication performance was improved by this technique, and it was confirmed that there was a performance improvement of up to 78.93% compared to the existing algorithm through BFM simulation.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.04a
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• pp.119-122
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• 2012

이종 멀티코어 프로세서는 각기 상이한 마이크로아키텍처, 캐시 사이즈, 클록 주파수를 갖는 다수의 코어 또는 프로세싱 유닛으로 이루어진 마이크로프로세서이다. 저에너지 소비가 산업계의 키워드로 부상하고 있는 이 시기에 이종 멀티코어는 동종 멀티코어보다 더 낮은 전력을 소비하고 성능면에서도 더 나은 프로세서로 주목받고 있다. 하지만, 동종 멀티코어에서의 동작을 가정하는 현재의 운영체제의 작업 스케줄러로는 이종 멀티코어의 이종적인 특성을 잘 활용할 수 없다. 본 논문에서는 이종 멀티코어 프로세서 작업 스케줄링에 관한 연구를 다면적으로 분석하여 각 방법의 장점과 단점을 개략적으로 정리하고 관련된 이슈들을 살펴보고자 한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.877-880
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• 2009

반도체 집적도의 향상과 제한된 프로세서 설계 능력으로 인한 칩 멀티 프로세서의 도입은 최근 수 년 동안 급속히 이루어졌으나, 다수의 프로세싱 코어를 효율적으로 사용하기 위한 기법은 부족한 실정이다. 칩 멀티 프로세서 상에서 실제 작업을 수행하지 않는 유휴 코어의 발생은 불가피하며, 이 때 코어가 소유한 자원들은 낭비될 수 밖에 없다. 기존의 연구들은 이렇게 낭비되는 자원 중에서 캐시의 효율적 관리를 위해 공유 캐시 형태로 캐시를 구성하였으나, 전체 캐시 관리에 따른 많은 오버헤드를 수반하였다. 본 논문에서는 이러한 유휴 캐시의 발생이 불가피함을 인지하고 그것을 칩 내 메모리 공간으로써 활용하여 칩 멀티 프로세서 전체의 성능을 향상시키는 기법을 제안한다. 이를 위해 ARM 코어 기반의 칩 멀티프로세서 시뮬레이터 환경을 구성하여 제안된 기법을 검증한다. 실험 결과 본 논문에서 소개된 기법은 4-코어 및 16 코어 기반 칩 멀티 프로세서 환경에서 각각 17%와 8%의 IPC 향상을 가져왔다.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.3
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• pp.339-349
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• 2017

This paper proposes a four-stage algorithm for detecting lanes on a driving car. In the first stage, it extracts region of interests in an image. In the second stage, it employs a median filter to remove noise. In the third stage, a binary algorithm is used to classify two classes of backgrond and foreground of an input image. Finally, an image erosion algorithm is utilized to obtain clear lanes by removing noises and edges remained after the binary process. However, the proposed lane detection algorithm requires high computational time. To address this issue, this paper presents a parallel implementation of a real-time line detection algorithm on a multi-core architecture. In addition, we implement and simulate 8 different processing element (PE) architectures to select an optimal PE architecture for the target application. Experimental results indicate that 40×40 PE architecture show the best performance, energy efficiency and area efficiency.

• Journal of the Korea Society of Computer and Information
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• v.19 no.9
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• pp.21-31
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• 2014

Singular value decomposition (SVD) has been widely used to identify unique features from a data set in various fields. However, a complex matrix calculation of SVD requires tremendous computation time. This paper improves the performance of a representative one-sided block Jacoby algorithm using a two-dimensional (2D) multi-core system. In addition, this paper explores an optimal multi-core system by varying the number of processing elements in the 2D multi-core system with the same 400MHz clock frequency and TSMC 28nm technology for each matrix-based one-sided block Jacoby algorithm ($128{\times}128$, $64{\times}64$, $32{\times}32$, $16{\times}16$). Moreover, this paper demonstrates the potential of the 2D multi-core system for the one-sided block Jacoby algorithm by comparing the performance of the multi-core system with a commercial high-performance graphics processing unit (GPU).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.8
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• pp.722-730
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• 2014

Due to the advance of hardware, various devices have mobility features, and many applications need the data transmission. In addition, it is essential for latest smartphones to utilize multi-cores and multi-threads because of the enhancement of Application Processor. Therefore, this paper analyzes the performance/power consumption according to transmission rate, the number of cores, and that of threads in the system that is supposed to conduct data transmission and processing simultaneously. Through the analysis, this paper provides a direction for the proper number of threads in terms of performance improvement and efficient power consumption.

• The KIPS Transactions:PartA
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• v.18A no.1
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• pp.1-10
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• 2011

Physical modeling has been widely used for sound synthesis since it synthesizes high quality sound which is similar to real-sound for musical instruments. However, physical modeling requires a lot of parameters to synthesize a large number of sounds simultaneously for the musical instrument, preventing its real-time processing. To solve this problem, this paper proposes a single instruction, multiple data (SIMD) based multi-core processor that supports real-time processing of sound synthesis of gayageum which is a representative Korean traditional musical instrument. The proposed SIMD-base multi-core processor consists of 12 processing elements (PE) to control 12 strings of gayageum in which each PE supports modeling of the corresponding string. The proposed SIMD-based multi-core processor can generate synthesized sounds of 12 strings simultaneously after receiving excitation signals and parameters of each string as an input. Experimental results using a sampling reate 44.1 kHz and 16 bits quantization show that synthesis sound using the proposed multi-core processor was very similar to the original sound. In addition, the proposed multi-core processor outperforms commercial processors(TI's TMS320C6416, ARM926EJ-S, ARM1020E) in terms of execution time ($5.6{\sim}11.4{\times}$ better) and energy efficiency (about $553{\sim}1,424{\times}$ better).