• Journal of the Korean Society for Precision Engineering
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• v.23 no.4 s.181
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• pp.153-161
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• 2006

Micro-forming is a suited technology to manufacture very small metallic parts(several $mm{\sim}{\mu}m$). Micro-forming of $Zr_{62}Cu_{17}Ni_{13}Al_8$ bulk metallic glass(BMG) as a candidate material for this developing process are feasible at a relatively low stress in the supercooled liquid state without any crystallization during hot deformation. In this study, micro- formability of a representative bulk metallic glass, $Zr_{62}Cu_{17}Ni_{13}Al_8$. was investigated for micro-forging of U-shape pattern. Micro-formability was estimated by comparing $R_f$ values ($=A_f/A_g$), where $A_g$ is cross-sectional area of U groove, and $A_f$ the filled area by material. Micro-forging process was simulated and analyzed by applying finite element method. FEM simulation results showed reasonable agreement with the experimental results when the material properties and simulation conditions such as top die speed, remeshing criteria and boundary conditions were tightly controlled. The micro-formability of $Zr_{62}Cu_{17}Ni_{13}Al_8$ was increased with increasing load and time in the temperature range of the supercooled liquid state. Also, FEM simulation using a commercial software, DEFORM was confirmed to be applicable for the optimization of micro-forming process.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.9-14
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• 2007

In this study, the thermal reliability on flip chip package with non-conductive pastes (NCPs) was evaluated under accelerated conditions. As the number of thermal shock cycle and the dwell time of temperature and humidity condition increased, the electrical resistance of the flip chip package with NCPs increased. These phenomenon was occurred by the crack between Au bump and Au bump and the delamination between chip or substrate and NCPs during the thermal shock and temperature and humidity tests. And the variation of electrical resistance during temperature and humidity test was larger than that during thermal shock test. Therefore it was identified that the flip chip package with NCPs was sensitive to environment with moisture.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.49-56
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• 2007

Effects of post-baking treatment conditions on the interfacial adhesion between electroless plated Ni and polyimide film were evaluated using $180^{\circ}C$ peel test. Measured peel strength values monotonically decrease from $38.6{\pm}1.1g/mm\;to\;26.8{\pm}2.2g/mm$ for the variations of post-baking treatment temperatures from $80^{\circ}C\;to\;180^{\circ}C$, respectively. Wet chemical treatment on the polyimide surface produces carboxyl and amide functional groups on the surface which is closely related to the change in interfacial adhesion between electroless Ni and polyimide films. It is speculated that interfacial adhesion seems to be controlled by carbonyl oxygen bonding near cohesive failure region during post-baking treatment.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.33-37
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• 2008

A noticeable amount of Kirkendall voids formed at the Sn-3.5Ag solder joint with electroplated Cu, and that became even more significant when an additive was added to Cu electroplating bath. With SPS, a large amount of voids formed at the $Cu/Cu_3Sn$ interface of the solder joint during thermal aging at $150^{\circ}C$. The in-situ AES analysis of fractured joints revealed S segregation on the void surface. Only Cu, Sn, and S peaks were detected at the fractured $Cu/Cu_3Sn$ interfaces, and the S peak decreased rapidly with AES depth profiling. The segregation of S at the $Cu/Cu_3Sn$ interface lowered interface energy and thereby reduced the free energy barrier for the Kirkendall void nucleation. The drop impact test revealed that the electrodeposited Cu film with SPS degraded drastically with aging time. Fracture occurred at the $Cu/Cu_3Sn$ interface where a lot of voids existed. Therefore, voids occupied at the $Cu/Cu_3Sn$ interface are shown to seriously degrade drop reliability of solder joints.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.1
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• pp.23-29
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• 1999

An yttria-stabilized zirconia(YSZ) thin film on a porous NiO-YSZ substrate for an anode support type solid oxide fuel cell(SOFC) was prepared by an electrophoretic deposition(EPD). Deposition condition and film properties in order to obtain the homogeneous YSZ thin film from the EPD solution with different polarity were studied. In different case of alcohol solution, hydrogen gas was produced in aqueous solution from the electrolyte reaction under constant current above 0.138 mA /$\textrm{cm}^2$.Its reaction generated the bubble-formed defect in the deposited film and decreased weight of the film. The homogeneous YSZ thin film was formed in alcohol solution at a constant current, 0.035 mA /$\textrm{cm}^2$ for 10 s.

• Proceedings of the Korea Technical Association of the Pulp and Paper Industry Conference
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• 2002.05a
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• pp.56-56
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• 2002

제지산업의 발전에 따라 치환도가 다른 여러 가지 용도의 양성 전분이 개발되어 적 용되고 있다. 특히 보류제로서 양성전분을 사용할 경우 보류 향상과 더불어 강도개선 효과를 동시에 얻을 수 있는 이점을 지니고 었다. 하지만 용수 조건의 악화, 미세분 함 량의 증가 등과 같은 점차 열악해지는 초지공정에 적용하기 위해서는 보다 높은 치환 도의 전분이 요구 되고 있다. 이에 본 연구에서는 고치환 양성 전분이 초지계 내에 첨가되었올 경우 나타나는 홉 착 특성을 파악하고, 보류 및 탈수 성능을 평가함으로서 올바른 적용 방법을 제시하고 적용 효율의 극대화를 모색하고자 하였다. 산-염기 세척과정을 거쳐 제조한 활엽수 BKP를 이용해 지료를 조성하고, DDA

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.173-176
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• 2002

B $i_{3.3}$L $a_{0.7}$ $Ti_{3}$ $O_{12}$(BLT) 강유전체 박막을 Pt/Ti/ $SiO_2$/Si 기판위에 졸-겔법 (sol-gel method) 으로 스핀코팅하여 Metal-Ferroelectric-Metal(MFM) 구조의 커패시터를 형성하였다. BLT 박막의 결정성은 후속열처리 온도가 증가할수록 향상되었으며 $R_{근}$값은 as~coated된 BLT 박막의 경우 3.8$\AA$를 나타내었으나 열처리 온도를 $700^{\circ}C$로 증가한 경우 12.9$\AA$으로 거칠은 표면형상으로 변화되었다. $650^{\circ}C$로 열처리된 BLT 박막의 잔류분극 2Pr ($\pm$($P^{*}$ -$P^{ ^}$))값은 5V 인가전압에서 약 29.1 $\mu$C/$cm^2$을 나타내었다. 또한 $10^{10}$ 스위칭 cycles 가지 분극 스위칭을 반복한 후에도 뚜렷한 잔류분극의 변화를 발견할 수 없어서 우수한 피로특성을 나타내었다. 3V 전압에서 BLT 박막의 누설전류는 약 2.2$\times$$10^{-8}$ A/$cm^2$를 나타내었다.내었다.었다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.241.2-241.2
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• 2011

다공 소재는 큰 비표면적과 규칙적으로 정렬된 구조의 특성으로 인해 자성메모리 소자용 재료, 나노 와이어 제작용 템플릿, 마이크로 반응기, 메타물질용 소재 등으로 각광을 받고 있다. 자기조립 수직배열 다공구조 재료를 제작하는 방법으로 흔히 알루미늄의 양극산화 방법과 이원공정계의 상분리 방법이 등이 있다. 본 연구에서는 상변태를 비롯한 패턴형성과 계면 운동을 가장 정확하게 다루는 이론적 모델로 알려진 상장모델(Phase Field model)을 이용하여 이원공정계의 박막성장과정 동안의 자발적 상분리에 의한 수직배열 자기조립 다공구조 형성을 시뮬레이션 한다. 상장모델을 기초로 하여 상분리 메커니즘에 의해 발현된 미세조직을 해석하고 다양한 공정변수가 미세조직 발현에 미치는 영향에 대해 연구한다. 또한 상장모델을 통해 얻은 결과는 기존에 발표된 연구들의 결과와 비교를 통해 유효성을 입증한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.96-96
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• 2013

전기습윤이란 고체 표면에 형성된 액적에 전기장을 인가하게 되면 액적과 표면의 계면에너지 감소로 인해 접촉각이 변화되는 현상을 말한다. 이 현상은 전자종이 구현에 응용이 모색되고 있으며, 다초점 렌즈, 마이크로 프리즘, 반사형 디스플레이 등에도 응용될 수 있다. 전기습윤현상의 응용 가능성이 현실화됨에 따라 최근 여러 표면에서의 전기습윤 현상이 연구되고 있다. 예를 들면, 나노 구조로 형성된 실리콘 기판에서 molten salt (1-ethyl-3-methyl-1-H-imidazolium tetrafluoroborate)에 22 V를 인가하면 약 $180^{\circ}$에서 $110^{\circ}$로 접촉각변화를, cyclopentanol에 50 V를 인가하면 표면에 완전히 퍼지는 현상이 보고된 바 있고, 배열된 Carbon Nanotube 박막에서는 탈이온수와 0.03 M NaCl 용액에 대해서 0~50 V를 가해줌에 따라 각각 $155^{\circ}$에서 $90^{\circ}$, $130^{\circ}$에서 $50^{\circ}$로의 접촉갑 변화가 있음이 관찰되었다. 본 연구에서는 화학적으로 안정하고 그 활용도가 매우 광범위한 실리카 코팅층을 전기분무증착법(electrospray deposition)을 이용해 형성하고, 코팅층의 표면 거칠기와 구조, 전기절연층의 두께 등에 따른 전기습윤 현상 거동을 조사하였다.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.3 s.40
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• pp.13-17
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• 2006

Dense and periodic arrays of holes and tungsten none dots were fabricated on silicon oxide and silicon. The holes were approximately 25 nm wide, 40 nm deep, and 60 nm apart. To obtain nano-size patterns, self-assembling resists were used to produce layer of hexagonally ordered parallel cylinders of polymethylmethacrylate(PMMA) in polystyrene(PS) matrix. The PMMA cylinders were degraded and removed with acetic acid rinse to produce a PS mask for pattern transfer. The silicon oxide was removed by fluorine-based reactive ion etching(RIE). Selectively deposited tungsten nano dots were formed inside nano-sized trench by using a low pressure chemical vapor deposition(LPCVD) method. Tungsten nano dot and trenched silicon sizes were 26 nm and 30 nm, respectively.