• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.9
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• pp.1-8
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• 1999

In this paper, we propose and analyze a concatenated coding scheme for DS/CDMA systems in asynchronous channels. In the concatenated coding, bandwidth efficient $2^{2L-2}$-state ${\frac{L}{L+1}}$-rate 2-MTCM with biorthogonal signal constellation is used for the inner code, and $(2^{L-1},\;{\lceil}\frac{2^{L-1}}{L/2}{\rceil})$ RS code is use for the outer code. It is shown that we can get considerable performance gain over the uncoded system without sacrificing the data transmission rate. The proposed system can be used as a coding scheme for reliable and high speed integrated information services of mobile communication systems.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.6
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• pp.1-5
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• 2011

We present the Multi-band orthogonal frequency division multiplexing ultra-wideband (MB-OFDM UWB) technology for increasing the transmission reach of wireless speaker systems. The proposed scheme adopts the Reed-Solomon coding for preventing the random error perfectly and shows the SNR gain in low bit error rate (BER) especially. So, we can increase the maximum reach of MB-OFDM UWB technology since the receiver sensitivity is improved. The simulation environment includes most effects of realistic channel environments such as Additive White Gaussian Noise (AWGN), CM1 channel model, Sampling frequency offset (SFO), Carrier frequency offset (CFO) to improve the simulation accuracy. The simulation results show that the proposed scheme can give a maximum 2 dB SNR gain and increase the transmission reach up to 12.6m.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4C
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• pp.365-373
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• 2003

In this paper, we design a versatle RS decoder which can decode RS codes of any block length n as well as any message length k, based on a modified Euclid's algorithm (MEA). This unique feature is favorable for a shortened RS code of any block length it eliminates the need to insert zeros before decoding a shortened RS code. Furthermore, the value of error correcting capability t can be changed in real time at every codeword block. Thus, when a return channel is available, the error correcting capability can be adaptiverly altered according to channel state. The decoder permits 4-step pipelined processing : (1) syndrome calculation (2) MEA block (3) error magnitude calculation (4) decoder failure check. Each step is designed to form a structure suitable for decoding a RS code with varying block length. A new architecture is proposed for a MEA block in step (2) and an architecture of outputting in reversed order is employed for a polynomial evaluation in step (3). To maintain to throughput rate with less circuitry, the MEA block uses not only a multiplexing and recursive technique but also an overclocking technique. The adaptive RS decoder over GF($2^8$) with the maximal error correcting capability of 10 has been designed in VHDL, and successfully synthesized in a FPGA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.12
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• pp.2394-2402
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• 2017

The frequency selective fading by multipaths determines a performance of underwater acoustic communication system in shallow littoral ocean. In this study, a characteristics of underwater acoustic channel and performance of multi-carrier system is evaluated in littoral ocean with a 50m deep water, an effective wave height of 0.5m and sandy mud bottom near Busan city. A multipath delay spread and time and frequency domain are presented as a function of a transmitter-to-receiver range. A bit-error-rate of a 5 channel 4FSK(Frequency Shift Keying) with a transmission rate of 1kbps, is examined and RS(Reed-Solomon) code is also adopted to remove a burst error due to time domain fading. A number of multipath are less than four and a bit-error-rate is decreased as an increase of a transmitter-to-receiver range which gives a congestion of multi-paths resulting in a decrease of time and frequency domain fading. The measured bit-error-rate is about 10-4 at greater than 600m of transmitter-to-receiver range.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.