• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2116-2120
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• 2007

A realization for image distortion correction processing system with DSP processor is presented in this paper. The image distortion correcting algorithm is realized by DSP processor for focusing on more real time processing than image quality. The lens and camera distortion coefficients are processed by the Lookup Tables and the correcting algorithm is applied to reverse mapping method for geometrical transform. The system experimentation results in the processing time about 31.3 msec $720{\times}480$ wide range image, and the image is stable and spontaneous to be about 8.3% average PSNR variation with changing a wide angle.

• Journal of IKEEE
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• v.23 no.2
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• pp.461-468
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• 2019

A continuous-time Delta-Sigma ADC has various benefits; it does not require an explicit anti-aliasing filter, and it is able to handle wider-band signals with less power consumption in comparison with a discrete-time Delta-Sigma ADC. However, it inherently needs to sample the signal with a high-speed clock, necessitating a complex decimation filter that operates at high speed in order to convert the modulator output to a low-rate high-resolution digital signals without causing aliasing. This paper proposes a continuous-time Delta-Sigma ADC architecture that employs pulse-width modulation and shows that the proposed architecture lends itself to a simpler implementation of the decimation filter using a lookup table.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.31 no.3
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• pp.527-532
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• 2021

In this paper, we propose an efficient finite field computation method for Rainbow algorithm, which is the only multivariate quadratic-equation based digital signature among the current US NIST PQC standardization Final List algorithms. Recently, Chou et al. proposed a new efficient implementation method for Rainbow on the Cortex-M4 environment. This paper proposes a new multiplication method over the finite field that can reduce the number of XOR operations by more than 13.7% compared to the Chou et al. method. In addition, a multiplicative inversion over that can be performed by a 4x4 matrix inverse instead of the table lookup method is presented. In addition, the performance is measured by porting the software to which the new method was applied onto RaspberryPI 3B+.

• Land and Housing Review
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• v.3 no.1
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• pp.59-68
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• 2012

The current land development cost price system is classified as the creating land by construction price and composition changes that occur sporadically in the process of completion at the source of the factors by incurred cost price. Housing for land cost price system is a lack of objectivity which scheme of the such a gap due to the land in accordance construction and incurred cost price system so far. Therefore, in order to increase the objectivity of costing the costing of predictable surprises should be reflected in the process. Under such a background, this study defined the effective differential ratio as the predictable, estimated them for various characteristics of each business district to reflect. For this, set the properties category of five types to attributes and making the complex category and Look-up table. Which result of model validation is showed a high reliability. Therefore, Continuous accumulation of material in the future, when them to reflect the construction cost, will contribute to the bridge the gap the construction cost between incurred them.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.102-107
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• 2007

This paper proposes a H.264/AVC entropy decoder without embedded processor nor memory fabrication process. Many researches on H.264/AVC entropy decoders require ROM or RAM fabrication process, which is difficult to be implemented in general digital logic fabrication process. Furthermore, many researches require embedded processors for bitstream manipulation, which increases area and power consumption. This papers proposes hardwired H.264/AVC entropy decoder without embedded processor, which improves data processing speed and reduces power consumption. Furthermore, its CAVLC decoder optimizes lookup table and internal buffer without embedded memory, which reduces hardware size and can be implemented in general digital logic fabrication process without ROM or RAM fabrication process. Designed entropy decoder was embedded in H.264/AVC video decoder, and it was verified to operate correctly in the system. Synthesized in TSMC 90nm fabrication process, its maximum operation frequency is 125MHz. It supports QCIF, CIF, and QVGA image format. Under slight modification of nC register and other blocks, it also support VGA image format.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.10
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• pp.1012-1015
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• 2011

The decision-directed blind equalization algorithm is often used due to its simplicity and good convergence property when the eye pattern is open. However, in a channel where the eye pattern is closed, the decision-directed algorithm is not guaranteed to converge. Hence, a modified Bussgang-type algorithm using a hyperbolic tangent function for zero-memory nonlinear(ZNL) function has been proposed and applied to avoid this problem by Filho et al. But application of this algorithm includes the calculation of hyperbolic tangent function and its derivative or a look-up table which may need a large amount of memory due to channel variations. To reduce the computational and/or hardware complexity of Filho's algorithm, in this paper, an improved method for the decision-directed algorithm is proposed. In the proposed scheme, the ZNL function and its derivative are respectively set to be the original signum function and a narrow rectangular pulse which is an approximation of Dirac delta function. It is shown that the proposed scheme, when it is combined with decision-directed algorithm, reduces the computational complexity drastically while it retains the convergence and steady-state performance of the Filho's algorithm.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.6
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• pp.602-611
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• 2004

Servo system has commonly adapted PI controller with fixed gains, because of its simplicity and determinative relationship among the parameters. The fixed gains PI system may be applied well to some operation conditions, but not non-linearities, complex and time variant operation conditions. For solving these problems, another conventional method, 'variable gun schedule according to speed', is published. The value of gain is determined according to the absolute value of the mover real speed. In this paper, FSTPIC(Fuzzy Self-Tuning PI Controller) is proposed based on various experiences to rapidly reduce speed error and to secure a good speed response characteristics. The effectiveness of proposed algorithms is demonstrated by comparing to two conventional gain systems via 4-quadrant operation.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.102-113
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• 2014

This paper suggests a novel hardware architecture of a real-time rectification which is to remove vertical parallax of an image occurred in the pre-processing stage of stereo matching. As an off-line step, Matlab Toolbox which was designed by J.Y Bouguet, was used to calculate calibration parameter of the image. Then, based on the Heikkila and Silven's algorithm, rectification hardware was designed. At this point, to enhance the precision of the rectified image, floating-point unit was generated by using Xilinx Core Generator. And, we confirmed that proposed hardware design had higher precision compared to other designs while having the ability to do rectification in real-time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.46-56
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• 1991

In this paper, 16word X 8bit Content Addressable and Reentrant Memory(CARM) is described. This device has 4 operation modes(read, write, match, reentrant). The read and write operation of CARM is like that of static RAM, CARM has the reentrant mode operation where the on chip garbage collection is accomplished conditionally. Thus function can be used for high speed matching unit of dynamic data flow computer. And CARM also can encode matching address sequentially according to therir priority. CARM consists of 8 blocks(CAM cell, Sequential Address Encoder(S.A.E). Reentrant operation. Read/Write control circuit, Data/Mask Register, Sense Amplifier, Encoder. Decoder). Designed DARM can be used in data flow computer, pattern, inspection, table look-up, image processing. The simulation is performed using the QUICKSIM logic simulator and Pspice circuit simulator. Having hierarchical structure, the layout was done using the 3{\;}\mu\textrm{m} n well CMOS technology of the ETRI design rule.

• Journal of the Korea Computer Graphics Society
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• v.14 no.2
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• pp.19-25
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• 2008

We synthesize a texture with different structures at different scales. Our technique is based on deterministic parallel synthesis allowing real-time processing on a GPU. A new coordinate transformation operator is used to construct a synthesized coordinate map based on different exemplars at different scales. The runtime overhead is minimal because this operator can be precalculated as a small lookup table. Our technique is effective for upsampling texture-rich images, because the result preserves texture detail well. In addition, a user can design a texture by coloring a low-resolution control image. This design tool can also be used for the interactive synthesis of terrain in the style of a particular exemplar, using the familiar 'raise and lower' airbrush to specify elevation.