• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.38 no.6
• /
• pp.665-674
• /
• 2001

In this paper, a reduced complexity fillet to simultaneously suppress the blocking and ringing artifacts of compressed video sequence is addressed. A new one dimensional regularized function to incorporate the smoothness to its neighboring pixels into the solution is defined, resulting in very low complexity filter The proposed regularization function consists of two sub-functions that combine local data fidelity and local smoothing constraints. The regularization parameters to control the trade-off between the local fidelity to the data and the smoothness are determined by available overhead information in decoder, such as maroc-block type and quantization step size. In addition, the regularization parameters are designed to have the limited range and stored as look-up-table, and therefore, the computational cost to determine the parameters can be reduced. The experimental results show the capability and efficiency of the proposed algorithm.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.19 no.3
• /
• pp.66-74
• /
• 2005

This paper presents an implementation of digital servo speed control system of SPMSM(Surface-mounted Permanent Magnet Synchronous Motor) for industrial application with Direct Torque Control(DTC) using TMS320F2812 DSP. Although, the vector control scheme is adapted in many industrial servo system, but the DSP calculation ratio is increased by reference frame transformation and SVPWM of vector control. Therefore, this paper investigate the possibility of DTC scheme for industrial servo drive system instead of vector control scheme. DSP calculation ratio is compared between vector control and DTC algorithm in addition to the characteristic of speed control response. The suggested SPMSM control system shows the possibility of DTC scheme for industrial servo motor drive system instead of a vector control algorithm.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.46 no.4
• /
• pp.116-123
• /
• 2009

Feature point matching, which is finding the corresponding points from two images with different viewpoint, has been used in various vision-based applications and the demand for the real-time operation of the matching is increasing these days. This paper presents a real-time feature point matching method by using a local descriptor derived by Zernike moments. From an input image, we find a set of feature points by using an existing fast corner detection algorithm and compute a local descriptor derived by Zernike moments at each feature point. The local descriptor based on Zernike moments represents the properties of the image patch around the feature points efficiently and is robust to rotation and illumination changes. In order to speed up the computation of Zernike moments, we compute the Zernike basis functions with fixed size in advance and store them in lookup tables. The initial matching results are acquired by an Approximate Nearest Neighbor (ANN) method and false matchings are eliminated by a RANSAC algorithm. In the experiments we confirmed that the proposed method matches the feature points in images with various transformations in real-time and outperforms existing methods.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38A no.4
• /
• pp.295-302
• /
• 2013

In the network coding, throughput can be increased by allowing the transformation of the received data at the intermediate nodes. However, the adversary can obtain more information at the intermediate nodes and make troubles for decoding of transmitted data at the sink nodes by modifying transmitted data at the compromised nodes. In order to resist the adversary activities, various information theoretic or cryptographic secure network coding schemes are proposed. Recently, a secure network coding based on the cryptographic hash function can be used at the random network coding. However, because of the computational resource requirement for cryptographic hash functions, networks with limited computational resources such as sensor nodes have difficulties to use the cryptographic solution. In this paper, we propose a new secure network coding scheme which uses linear transformations and table lookup and safely transmits n-1 packets at the random network coding under the assumption that the adversary can eavesdrop at most n-1 nodes. It is shown that the proposed scheme is an all-or-nothing transform (AONT) and weakly secure network coding in the information theory.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.18 no.11
• /
• pp.1701-1713
• /
• 1993

This paper proposes a simple and highly effective RACMC(Real-time ATM Cell Monitoring and Control) algorithm and the resulting bandwidth gain effects art considered. RACMC algorithm performs usage parameter controls according to the monitoring informations of input data cells generated from the accepted connections and the controlling informations set by the M/P(Management Plane) for that connection. The results of monitoring and controlling actions for ATM data cells are transmitted to the M/P and the control parameters in lookup table are updated according to the condition of currently used bandwith. Therefore, the proposed algorithm can allocate network resource optimally and solve the several tantalizing problems that the existing cell control algorithm have, that is, the difficulty in controlling as monitoring very bursty traffics, unavoidable processing delay, and limited input buffer size when implemented. By the performance analysis using computer simulation, RACMC algorithm proves to be very effective especially in ATM network as implemented simply.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.7 no.1
• /
• pp.81-90
• /
• 2002

This paper presents an Implementation of digital high-performance position sensorless control system of Reluctance Synchronous Motor(RSM) drives with Direct Torque Control(DTC). The system consists of stator flux observer, speed and torque estimator, two digital hysteresis controllers, an optimal switching look-up table, Insulated Gate Bipolar Transistor(IGBT) voltage source inverter, and TMS320C31 DSP board. The stator flux observer Is based on the combined voltage and current model with stator flux feedback adaptive control of which inputs are current and voltage sensed on motor terminal for wide speed range. In order to prove the suggested sensorless control algorithm for industrial field application, we have some simulation and actual experiment at low and high speed range. The developed high-performance speed control by fully digital system are shown a good response characteristic of control results and high performance features using 1.0[kW] RSM having 2.57 reluctance ratio of $L_d/L_q$.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.2
• /
• pp.439-446
• /
• 2011

In this paper, we proposed and implemented a dedicated hardware for Huffman coding which is a method of entropy coding to use compressing multimedia data with video coding. The proposed Huffman codec consists Huffman encoder and decoder. The Huffman encoder converts symbols to Huffman codes using look-up table. The Huffman code which has a variable length is packetized to a data format with 32 bits in data packeting block and then sequentially output in unit of a frame. The Huffman decoder converts serial bitstream to original symbols without buffering using FSM(finite state machine) which has a tree structure. The proposed hardware has a flexible operational property to program encoding and decoding hardware, so it can operate various Huffman coding. The implemented hardware was implemented in Cyclone III FPGA of Altera Inc., and it uses 3725 LUTs in the operational frequency of 365MHz

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.22 no.3
• /
• pp.495-504
• /
• 2012

This paper presents various speed optimization techniques for software implementation of the HIGHT block cipher on CPUs and GPUs. We considered 32-bit and 64-bit operating systems for CPU implementations. After we applied the bit-slicing and byte-slicing techniques to HIGHT, the encryption speed recorded 1.48Gbps over the intel core i7 920 CPU with a 64-bit operating system, which is up to 2.4 times faster than the previous implementation. We also implemented HIGHT on an NVIDIA GPU equipped with CUDA, and applied various optimization techniques, such as storing most frequently used data like subkeys and the F lookup table in the shared memory; and using coalesced access when reading data from the global memory. To our knowledge, this is the first result that implements and optimizes HIGHT on a GPU. We verified that the byte-slicing technique guarantees a speed-up of more than 20%, resulting a speed which is 31 times faster than that on a CPU.