• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.7
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• pp.1227-1234
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• 2008

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.11
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• pp.529-535
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• 2018

The range extender vehicle runs on a mechanism that allows the small power generation engine to start in the most efficient specific operating range to charge the battery and extend the mileage. In this study, we developed a step motor type intake air supply system that replaces existing throttle body system to develop a simple low cost control logic system. The system was applied to the existing base engine, and in order to improve the performance by increasing the amount of intake air, the effect of changing the length of the intake and exhaust manifold was experimentally examined. As a result, the Type B intake air control actuator operated by one step motor showed higher performance than the Type A in all the operation region, but the performance was lower than that of the base engine due to the increase of flow resistance. To improve this, it was confirmed that the engine performance was improved at both speeds of 2200rpm and 4300rpm when the 140mm adapter was installed in the intake manifold and when the newly designed 70mm exhaust manifold was applied. Through this process, high - precision operation control was realized by connecting the generator load to the optimized engine for the range extender electric vehicle. Experimental results showed that the speed change rate was within ${\pm}2.5%$ at 2200rpm in 1st stage and 4300rpm in 2nd stage and the speed follow-up result of 610 rpm/s was obtained when the speed was increased from 2200rpm to 4300rpm.

• Journal of Digital Convergence
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• v.17 no.7
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• pp.131-138
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• 2019

The world's electricity production ratio is 40% for coal, 20% for natural gas, 16% for hydroelectric power, 15% for nuclear power and 6% for petroleum. Fossil fuels also cause serious problems in terms of price and supply because of the high concentration of resources on the earth. Solar energy is attracting attention as a next-generation eco-friendly energy that will replace fossil fuels with these problems. In this study, we test the charge-operation plan and the discharge operation plan for peak-cut operation by applying the maximum power demand reduction simulation. To do this, we selected the electricity usage from November to February, which has the largest amount of power usage, and applied charge / discharge logic. Simulation results show that the contract power decreases as the peak demand power after the ESS Peak-cut service is reduced to 50% of the peak-target power. As a result, the contract power reduction can reduce the basic power value of the customer and not only the economic superiority can be expected, but also contribute to the improvement of the electric quality and stabilization of the power supply system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.1
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• pp.419-425
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• 2019

The objective of this study was to investigate the cooling performance characteristics of a hybrid refrigeration system in a heavy duty vehicle. The tested hybrid refrigeration system had additionally an electric compressor besides the present mechanical compressor for selective use according to the operating conditions. The applied electric compressor was a scroll type and with 18.0 cc displacement. In order to analyze the performance characteristics of the hybrid refrigeration system with respect to the cooling capacity and Coefficient of Performance (COP), other components, including two different types of compressors, were installed and tested under various operating conditions such as compressor speed and air flow rate of the evaporator. When the electric compressor was operated at 4,500 rev/min, the cooling capacity was about 4.0kW and COP was 3.5. When the mechanical compressor was operated, whereas the cooling capacity was higher than the electric controlled compressor, COP was lower due to the larger displacement and higher power consumption. To analyze the hybrid system operating characteristics due to reasonable cooling capacity with electric compressor operation, the mechanical compressor and electric compressor were operated by turns every 10 minutes under certain system operating conditions. Because surge pressure occurred when both compressors were switched on, the operating strategy required some time to balance the system pressure.

• Korean Journal of Construction Engineering and Management
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• v.20 no.1
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• pp.141-150
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• 2019

In the overseas plant construction market, the domain construction firms' construction capability has been greatly improved, but the capability of project management is evaluated to be insufficient compared to the technical aspect. Project management capabilities from the initial planning stage of project execution are regarded as the core competence of advanced construction companies. Among them, it is urgent to improve the capacity of conceptual estimate for domestic companies. In this study, the researchers surveyed and analyzed the methodology of estimating project cost in the planning phase of the plant project and developed an estimation method by conducting a case study analysis. Based on the logic of the cost index and parametric estimation method among the existing estimation methodology, the estimation tool was developed by deriving the input and output variables tailored to the plant project. The validity of the proposed methodology was evaluated by comparing the accuracy between the project estimate amount of the case project and the actual project amount. In order to increase the utilization of the developed conceptual estimate methodology,for plant construction project, it is necessary to systematize the data of the historical project data. Increasing the accuracy of future project cost estimates is directly related to increasing project award and profitability of the domestic construction company.

• Journal of IKEEE
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• v.22 no.4
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• pp.1012-1018
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• 2018

In this paper, CMOS SAR (Successive Approximation Register) A/D converter with 1.8V supply voltage is designed for IoT sensor processing. This paper proposes design of a 12-bit SAR A/D converter with two A / D converters in parallel to improve the sampling rate. A/D converter1 of the two A/D converters determines all the 12-bit bits, and another A/D converter2 uses the upper six bits of the other A/D converters to minimize power consumption and switching energy. Since the second A/D converter2 does not determine the upper 6 bits, the control circuits and SAR Logic are not needed and the area is minimized. In addition, the switching energy increases as the large capacitor capacity and the large voltage change in the C-DAC, and the second A/D converter does not determine the upper 6 bits, thereby reducing the switching energy. It is also possible to reduce the process variation in the C-DAC by proposed structure by the split capacitor capacity in the C-DAC equals the unit capacitor capacity. The proposed SAR A/D converter was designed using 0.18um CMOS process, and the supply voltage of 1.8V, the conversion speed of 10MS/s, and the Effective Number of Bit (ENOB) of 10.2 bits were measured. The area of core block is $600{\times}900um^2$, the total power consumption is $79.58{\mu}W$, and the FOM (Figure of Merit) is 6.716fJ / step.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.755-758
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• 2014

In this paper, we propose effective Deblocking Filter hardware architecture for High Efficiency Video Coding encoder. we propose Deblocking Filter hardware architecture with less processing time, filter ordering for low area design, effective memory architecture and four-pipeline for a high performance HEVC(High Efficiency Video Coding) encoder. Proposed filter ordering can be used to reduce delay according to preprocessing. It can be used for realtime single-port SRAM read and write. it can be used in parallel processing by using two filters. Using 10 memory is effective for solving the hazard caused by a single-port SRAM. Also the proposed filter can be used in low-voltage design by using clock gating architecture in 4-pipeline. The proposed Deblocking Filter encoder architecture is designed by Verilog HDL, and implemented by 100k logic gates in TSMC $0.18{\mu}m$ process. At 150MHz, the proposed Deblocking Filter encoder can support 4K Ultra HD video encoding at 30fps, and can be operated at a maximum speed of 200MHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.11-20
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• 2007

A fast Montgomery multiplication occupies important to the design of RSA cryptosystem. Montgomery multiplication consists of two addition, which calculates using CSA or RBA. In terms of CSA, the multiplier is implemented using 4-2 CSA o. 5-2 CSA. In terms of RBA, the multiplier is designed based on redundant binary system. In [1], A new redundant binary adder that performs the addition between two binary signed-digit numbers and apply to Montgomery multiplier was proposed. In this paper, we reconstruct the logic structure of the RBA in [1] for reducing time and space complexity. Especially, the proposed RB multiplier has no coupler like the RBA in [1]. And the proposed RB multiplier is suited to binary exponentiation as modified input and output forms. We simulate to the proposed NRBA using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is smaller by 18.5%, 6.3% and faster by 25.24%, 14% than 4-2 CSA, existing RBA, respectively. And Especially, the result is smaller by 44.3% and faster by 2.8% than the RBA in [1].

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.1
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• pp.134-145
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• 2021

It is common to optimize the propulsion control system through a so-called tuning process that modifies the parameter values of the propulsion control software during a ship commissioning. However, during this process, if the error of the initial setting value is large, the tuning time may take too long, or the propulsion equipment can be seriously damaged. Therefore, we conducted research on the design of a propulsion controller that applied a Processor lever controller even for inexperienced people with relatively little experience in tuning propulsion control software to be able to reduce the tuning time while protecting the propulsion system. Through simulation, by comparing the execution result of propulsion control lever commands through the PI controller without applying the Processor lever controller. We analyzed the improvement of the Overshoot and propulsion performance. The simulation results showed that the safety of the propulsion system increased because Overshoot of approximately 9.74%, which occurred when the Processor lever function was not applied.