• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.5
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• pp.66-76
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• 2000

This paper describes design and implementation of caption-processing ASIC(Application Specific Integrated Circuits) for OSD(On Screen Display) of karaoke system. The OSD of conventional karaoke system was implemented by a general purpose DSP, however this paper suggest a design to save hardware resources. The ASIC receives commands and data of graphic and caption from host processor, and then modifies the data to have various graphic effects. The design has been done by schematic and VHDL coding. The design was verified by logic simulation and FPGA emulation on the real system. The chip was fabricated with 0.8${\mu}{\textrm}{m}$ CMOS SOG, and worked properly at the karaoke system.

• KEPCO Journal on Electric Power and Energy
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• v.6 no.3
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• pp.253-257
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• 2020

The local information processing devices are devices that process information by converting voltage, current, and digital electric signals from legacy-type power facility into IEC 61850 based data. It acquires and processes the operation information of legacy-type power facility, performs control of power facility, and interlock function using internal logic. In particular, the time to convert data to process input and output information for a device is important because a number of protection relay input and output signals are handled by only one device. This paper introduces test methods and cases for measuring IEC 61850 communication function and input/output data conversion time of local information processing device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2633-2640
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• 2009

We design a small-area, low-power, and high-speed EEPROM for touch screen controller IC. As a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed, and high-voltage switching circuits repeated in the EEPROM core circuit are optimized. A digital data-bus sensing amplifier circuit is proposed as a low-power technology. For high speed, the distributed data-bus scheme is applied, and the driving voltage for both the EEPROM cell and the high-voltage switching circuits uses VDDP (=3.3V) which is higher than the logic voltage, VDD (=1.8V), using a dual power supply. The layout size of the designed 128-KBit EEPROMIP is $662.31{\mu}m{\times}1314.89{\mu}m$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.453-461
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• 2010

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of embedded RISC core and a clock-gating algorithm using ODC (Observability Don't Care) operation to improve the power consumption of the core. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC core applied the proposed architecture is improved about 29% and dynamic power of the core using Chartered $0.18{\mu}m$ technology library is reduced by 16%.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.6
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• pp.1639-1646
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• 2008

This study designed and realized a new type of RFID middle-ware based on .NET Compact Framework platform using PXA255 embedded board and Windows CE as operating system. The proposed embedded RFID middle-ware system controls via LAN a number of RFID sensors using RS-232 as interface and was designed on the basis of components of each function necessary RFID middle-ware. Application module operating in the SOA environment analyzes the data received from the RFID sensors with the embedded RFID middle-ware and in turn performs appropriate business logic. Client module to be used by end users can use RFID information in database, by web method call of application.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.6B
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• pp.710-719
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• 2011

Shipping companies have become interested in the development of strategic ship assets management systems which are implemented for high competitiveness and business rationalization to meet the tough business environment of high oil prices and decrease in cargo. In this paper we introduce a ship assets management system that is suitable for the SAN(Ship Area Network) environment. This system is designed to execute business strategy of ship owners giving consideration to requirements of shipping stakeholders. In addition we have implemented it in a web-based ERP system (SHERP) which separates user interface and business logic. The SHERP is based on STEP and PLIB, which are international standards for data exchange of mechanical devices and parts. It also adopts a ship ontology to manage the ship information and knowledge during its life-cycle. The SHERP will be a concrete example of servitization of shipbuilding, as an information system which is used in ships and ship groups.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.9A
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• pp.924-933
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• 2008

This paper proposes a novel LDPC code decoder architecture to improve throughput for DVB-S2, a second generation standard of ETSI for satellite broad-band applications. The proposed architecture clusters 360 bitnodes and checknodes into groups utilizing the property of IRA-LDPC code. Functional modules which perform calculations for bitnode groups and checknode groups have local memories and store the messages from the other type of functional modules connected by edges at their local memories. The proposed architecture can avoid memory conflicts by accessing stored messages sequentially, hence, increases throughput in the proposed DVB-S2 LDPC code decoder architecture. The proposed architecture was synthesized using the TSMC 90nm technology. Synthesis results show that throughput of the proposed architecture is improved by 104% and 478%, respectively, when compared with those of the architectures proposed by F. Kienle and J. Dielissen.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.10
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• pp.1317-1327
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• 2016

The baggage handling system (BHS) is one of the most complex system in the airport. A highly economical operating system is required to ensure its performance in consideration of its enormous cost on the extension. Furthermore, the inefficient operation deteriorates not only the system performance but the imbalance among the check-in counters because of a bottleneck on the conveyors downstream. The objective of this research is to improve the performance of both the BHS and the check-in area by efficiently controlling the flow in the merging area on the conveyors. Thus, we suggest a control logic of which the concept is borrowed from data networks. The simulation is used to analyze impacts of the conveyors bottleneck on the check-in area and optimize some parameters used in the suggested logic. We also discuss some observations from the simulation results into several aspects of performance measures.

• The KIPS Transactions:PartA
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• v.11A no.5
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• pp.333-340
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• 2004

In order that routers forward a packet to its destination, they perform IP address lookup which determines the next hop according to the packet's destination address. In designing high speed routers, IP address lookup is an important issue. In order to design high speed routers, this paper proposes a parallel IP lookup scheme which consists of several IP lookup engines without any modification of already fabricated indirect IP lookup chipsets. Also, we propose a simple rule for partitioning IP prefix entries In an overall forwarding table among several IP lookup engines. And we evaluate the performance of the proposed scheme in terms of the memory size required for storing lookup information and the number of memory accesses on constructing the forwarding table. With additional hardware logics, the proposed scheme can reduce about 30% of the required memory size and 80% of the memory access counts.

• The KIPS Transactions:PartD
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• v.9D no.4
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• pp.619-628
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• 2002

Reusable software component is an ultimate goal for the software development. Component based development is focused on advanced concepts rather than passive manipulation or class library with source codes. However, the primary component construction in component based development lead to an additional development cost and effort for reconstructing the new software component within a component model. Java application provides several features based on component model. But, we only have an opportunity to develop the smallest reuse units or the restricted set of GUI components. It cannot contributed as a component and only used in the specific domain component with high cost and efforts. In this paper, we apply java component model to the existing java application and extract javabeans through extending the component scalability. We also discuss the algorithm for transformation mechanism from legacy class to javabeans with a partial of business logic.