• Proceedings of the KIEE Conference
• /
• 2008.10b
• /
• pp.251-252
• /
• 2008

Type-2 퍼지 집합은 Type-1 퍼지 집합에서는 다루기 어려운 언어적인 불확실성을 더욱 효과적으로 다룰 수 있다. TSK 퍼지 로직 시스템(TSK Fuzzy Logic Systems; TSK FLS)은 후반부를 1차 및 2차 함수식으로 나타내며 Mamdani 모델과 함께 가장 널리 사용되는 모델이다. 본 연구의 Interval Type-2 TSK FLS은 전반부에서 Type-2 퍼지 집합을 이용하고 후반부는 계수가 Type-1 퍼지집합인 1차식을 사용한다. 또한 전반부는 가우시안 형태의 Type-2 멤버쉽 함수를 사용하며, 오류역전파 학습알고리즘을 사용하여 파라미터들을 최적화 한다. 또한 학습에 앞서 PSO(Particle Swarm Optimization) 알고리즘을 사용하여 최적 학습률을 찾아 모델의 학습능력을 보다 효율적으로 한다. 본 논문에서는 Type-1과 Type-2 FLS의 성능을 가스로 공정 데이터를 적용하여 두 모델의 성능을 비교하고 노이즈를 추가한 데이터를 이용하여 노이즈에 대한 성능도 비교 분석한다.

• Nuclear Engineering and Technology
• /
• v.27 no.6
• /
• pp.894-897
• /
• 1995

원자력 발전소의 안전계통은 요구된 신뢰도를 확보하기 위하여 각 트립 변수(공정계통 및 핵관련 총11개)회로의 센서 및 트립로직으로 구성된 각자의 채널에 대하여 주기적으로 운전중에 운전원에 의해 수동으로 수행하므로 안전계통에 대한 신뢰도를 화보하고 있다. 안전계통에 대한 시험자동화는 컴퓨터에 의해 시험 신호의 발생과 시험 결과의 표시 및 기록이 자동적으로 프로그램에 의해서 수행되는 것을 의미하며, 시험 자동화에 의해 주기 시험에 따른 시험시간 단축과 운전원의 심리적 부담을 경감하여 운전원에 의한 인적 실수 방지 및 계통 신뢰도 향상에 기여하는 것은 물론 계통을 단순화하고 기기경비의 절감 효과를 가져온다. 현재 기존 중수로 발전소는 직접 시험 방식에 의해 모의 신호를 시험 대상 채널의 센서부분에 보내어 안전 계통을 시험하여 해당 루프에 대한 건전성을 점검하고 있는데, 이 방식은 시험회로가 복잡하여 이로인한 기기의 설치 경비 상승, 유지 보수의 부담 증가 및 운전원의 주기 시험에 대한부담감으로 인적 실수를 유발하는등 계통 신뢰도 저하의 문제점이 지적되어 개선이 요구된다.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2000.05a
• /
• pp.708-713
• /
• 2000

A research on the AFC(Auto Feedrate Control) by a fuzzy controller using a tool dynamometer and motor currents was conducted. For simulations, cutting dynamics of end-milling process was modeled by geometric relationship between tool and work-piece. The fuzzy logic controller was employed to track the desired cutting force and showed good performance in simulations and several experiments. The spindle motor currents was modeled to estimate cutting force and successfully used for the AFC.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 2008.04a
• /
• pp.321-324
• /
• 2008

Type-2 퍼지 집합은 Type-1 퍼지 집합에서는 다루기 어려운 언어적인 불확실성을 더욱 효과적으로 다룰 수 있다. TSK 퍼지 로직 시스템(TSK Fuzzy Logic Systems; TSK FLS)은 Mamdani 모델과 함께 가장 널리 사용되는 FLS이다. 본 연구의 Interval Type-2 TSK FLS 모델은 전반부에서 Type-2 퍼지 집합을 이용하고 후반부는 계수가 상수인 1차식을 사용한다. 전반부의 파라미터는 오류역전파 방법(Back-propagation)을 통한 학습으로 결정되고, 후반부 파라미터(계수)들은 Least squre method(LSM)를 사용하여 결정된 값을 사용하여 모델을 구축한다. 본 논문에서는 Type-1 TSK FLS과 Type-2 TSK FLS의 성능을 가스로 공정 데이터를 적용하여 비교 분석한다. 또한 랜덤 화이트 가우시안 노이즈를 추가한 테스트 데이터를 사용하여 노이즈에 대한 성능을 분석한다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.19 no.11
• /
• pp.994-999
• /
• 2006

For low-cost embedded EEPROM, in this paper, single polysilicon EEPROM and n-channel high-voltage LDMOST device are developed in a $0.25{\mu}m$ standard CMOS logic process. Using these devices developed, the EEPROM chip is fabricated. The fabricated EEPROM chip is composed of 1 Kbit single polysilicon EEPROM away and high voltage driver circuits. The program and erase characteristics of the fabricated EEPROM chip are evaluated using 'STA-EL421C'. The fabricated n-channel high-voltage LDMOST device operation voltage is over 10 V and threshold voltage window between program and erase states of the memory cell is about 2.0 V.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.3
• /
• pp.699-707
• /
• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of IKEEE
• /
• v.14 no.3
• /
• pp.190-198
• /
• 2010

This paper describes a auto focus piezo actuator driver IC for portable digital camera. The 80[V] DC voltage is generated by a DC-DC converter and supplied to power of piezo moving control circuit. The voltage of piezo actuator needs range -20[V] to 80[V] proportional to 1[Vp-p] input control voltages. The dimensions and number of external parts are minimized in order to get a smaller hardware size. IIC(Inter-IC) interface logic is designed for data interface and it makes debugging easy, test for mass productions. The power consumption is around 40[mW] with supply voltage of 3.6[V]. This device has been fabricated in a 0.6[um] double poly, triple metal 100[V] BCD MOS process and whole chip size is 1600*1500 [$um^2$].

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.7
• /
• pp.1371-1378
• /
• 2009

We propose a low-power eFuse one-time programmable (OTP) memory cell based on a logic process. The eFuse OTP memory cell uses separate transistors optimized at program and read mode, and reduces an operation current at read mode by reducing parasitic capacitances existing at both WL and BL. Asynchronous interface, separate I/O, BL SA circuit of digital sensing method are used for a low-power and small-area eFuse OTP memory IP. It is shown by a computer simulation that operation currents at a logic power supply voltage of VDD and at I/O interface power supply voltage of VIO are 349.5${\mu}$A and 3.3${\mu}$A, respectively. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18${\mu}$m generic process is 300 ${\times}$557${\mu}m^2$.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.4
• /
• pp.913-920
• /
• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.1
• /
• pp.183-190
• /
• 2010

We propose an eFuse one-time programmable (OTP) memory cell based on a logic process, which is programmable by an external program voltage. For the conventional eFuse OTP memory cell, a program datum is provided with the SL (Source Line) connected to the anode of the eFuse going through a voltage drop of the SL driving circuit. In contrast, the gate of the NMOS program transistor is provided with a program datum and the anode of the eFuse with an external program voltage (FSOURCE) of 3.8V without any voltage drop for the newly proposed eFuse cell. The FSOURCE voltage of the proposed cell keeps either 0V or the floating state at read mode. We propose a clamp circuit for being biased to 0V when the voltage of FSOURCE is in the floating state. In addition, we propose a VPP switching circuit switching between the logic VDD (=1.8V) and the FSOURCE voltage. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's $0.15{\mu}m$ generic process is $359.92{\times}90.98{\mu}m^2$.