• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1953-1955
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• 1999

The effects of the local lifetime control on the characteristics of IGBT are investigated using the 2-dimensional device simulator, MEDICI. Many lumped resistive turn-off simulations are carried out to analyze the effects of the minority carrier lifetime, the width, and the position of the region with a reduced local minority carrier lifetime. As a result of these simulations, it is concluded that the on state voltage drop$(V_{CE,SAT})$ is only slightly increased while the switching behavior is greatly improved if the low lifetime region is properly set. And these results are compared with IGBTs having uniform lifetime.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1111-1113
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• 1995

To improve latch up characteristics of IGBT, this paper proposed new structure with reverse channel. IGBT proposed by this paper were designed on SOI substrate, $p^+$-substrate, and $n^+$-substrate, respectively. As a result of the simulation, we had achieved high latch up voltage and high conduction current density at IGBT with proposed structure. Latch up voltage of Conventional IGBT was 2.5V but IGBT with proposed structure was latched up at $5{\sim}94V$, respectively. And was showed high conduction current desity($10^4{\sim}10^7A/cm^2$)

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.161-165
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• 2004

In this paper, an 8bit wave pipelined adder using the static CMOS plus Edge-Sensing Completion Detection Logic is presented. The clockless wave-pipelining algorithm was implemented in the circuit design. The Edge-Sensing Completion Detection (ESCD) in the algorithm is consisted of edge-sensing circuits and latches. Using the algorithm, skewed data at the output of 8bit adder could be aligned. Simulation results show that the adder operates at 1GHz in $0.35{\mu}m$ CMOS technology with 3.3V supply voltage.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2013.05a
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• pp.214-214
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• 2013

Diamond like carbon(DLC) 박막은 고경도, 저마찰, 내스크래치 특성을 요구하는 표면기술 응용분야에 널리 사용되며, 대면적 저가 코팅 방법 개발 및 물성 조절 기술이 요구된다. 본 연구에서는 Filtered Vacuum Arc (FVA)를 통해 증착되는 Hydrogen-free DLC 박막의 밀착력 제어를 위한 증착시 기판 전압에 따른 증착 및 밀착력 특성을 분석하였다. 기판전압이 0~-150 V 까지 변화함에 따른 스크래치 테스트 결과를 통해 최적 증착 조건을 도출하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.9
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• pp.551-554
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• 2014

This paper was showed latch up characteristics of super junction power MOSFET by parasitic thyristor according to trench etch angle. As a result of research, if trench etch angle of super junction MOSFET is larger, we obtained large latch up voltage. When trench etch angle was $90^{\circ}$, latch up voltage was more 50 V. and we got 700 V breakdown voltage. But we analyzed on resistance. if trench etch angle of super junction MOSFET is larger, we obtained high on resistance. Therefore, we need optimal point by simulation and experiment for solution of trade off.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.11
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• pp.686-689
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• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.10
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• pp.75-79
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• 2013

The automatic quiescent power cut-off receptacles(QPCR from now on) have achieved a noticeable energy saving so far. The government is preparing a new code for wider promotion of the QPCRs. This paper presents a new QPCR that adopts the latch relay instead of the conventional coil-operated relay. Measurement results of the prototype have shown up to 0.22W improvement of quiescent power compared with existing products.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.44-44
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• 2001

본 논문에서는 CMOS로 구현된 3.3V 8-bit 200MSPS의 Folding / Interpolation 구조의 A/D 변환기를 제안한다. 회로에 사용된 구조는 FR(Folding Rate)이 8, NFB(Number of Folding Block)가 4, Interpolation rate 이 8이며, 분산 Track and Hold 구조를 회로를 사용하여 Sampling시 입력주파수를 Hold하여 높은 SNDR을 얻을 수 있었다. 고속동작과 저 전력 기능을 위하여 향상된 래치와 디지털 Encoder를 제안하였고 지연시간 보정을 위한 회로도 제안하였다. 제안된 ADC는 0.35㎛, 2-Poly, 3-Metal, n-well CMOS 공정을 사용하여 제작되었으며, 유효 칩 면적은 1070㎛×650㎛ 이고, 3.3V전압에서 230mW의 전력소모를 나타내었다. 입력 주파수 10MHz, 샘플링 주파수 200MHz에서의 INL과 DNL은 ±1LSB 이내로 측정되었으며, SNDR은 43㏈로 측정되었다.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.160-163
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• 2000

In this paper, we propose an efficient technique to minimize the input offset of a dynamic latch comparator. We analyzed offset due to charge injection mismatching and unwanted positive feedback during sampling phase. The last one was only considered in the previous works. Based on the analysis, we proposed a modified dynamic latch with initialization switch. The proposed circuit was simulated using 0.65$\mu\textrm{m}$ CMOS process parameter with 5v supply. The simulation results showed that the input offset is less than 5mv at 200㎒ sampling frequency and the input offset is improved about 80% compared with previous work in 5k$\Omega$ input resistance.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.9
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• pp.47-54
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• 2003

In this study, to achieve the optimal conditions for mechanical hyper-fine pattern fabrication process, deformation behavior of the materials during indentation was studied with numerical method by ABAQUS S/W. Polymer (PMMA) and brittle materials (Si, Pyrex glass) were used as specimens, and forming conditions to reduce the elastic re cover and pile-up were proposed. The indenter was modeled a rigid surface. Minimum mesh sizes of specimens are 1 -l0nm. Comparison between the experimental data and numerical result demonstrated that the finite element approach is capable of reproducing the loading-unloading behavior of a nanoindentation test. The result of the investigation will be applied to the fabrication of the hyper-fine pattern.