• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• Journal of Broadcast Engineering
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• v.22 no.3
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• pp.350-365
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• 2017

Steganography is a technique for secret data communication, which is not perceived by third person between a receiver and a transmitter. It has been developed for thousands of years for the transmission of military, diplomatic or business information. The development of digital media and communication has led to the development of steganography techniques in modern times. Technic of image steganography include the LSB, which fixes the number of embedded bits into a pixel, and PVD, which exploits the difference value in the neighboring pixel pairs. In the case of PVD image steganography, a large amount of information is embedded fluidly by difference value in neighboring pixel pairs and the designed range table. However, since the secret information in order is embedded, if an error of the number of embedded bits occurs in a certain pixel pair, all subsequent information will be destroyed. In this paper, we proposes the method, which improve the vulnerability of PVD property about external attack or various noise and extract secret information. Experimental process is comparison analysis about stego-image, which embedded various noise. PVD shows that it is not possible to preserve secret information at all about noise, but it was possible to robustly extract secret information for partial noise of stego-image in case of the proposed PVD image steganography with locally-fixed number of embedding bits.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.2
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• pp.28-34
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• 2012

Various feature extraction algorithms are widely applied to real-time image processing applications for extracting significant features from images. Feature extraction algorithms are mostly combined with image processing algorithms mostly for image tracking and recognition. Feature extraction function is used to supply feature information to the other image processing algorithms and it is mainly implemented in a preprocessing stage. Nowadays, image processing applications are faced with embedded system implementation for a real-time processing. In order to satisfy this requirement, it is necessary to reduce execution time so as to improve the performance. Reducing the time for executing a feature extraction function dose not only extend the execution time for the other image processing algorithms, but it also helps satisfy a real-time requirement. This paper explains FAST (Feature from Accelerated Segment Test algorithm) of E. Rosten and presents FPGA-based embedded hardware accelerator architecture. The proposed acceleration scheme can be implemented by using approximately 2,217 Flip Flops, 5,034 LUTs, 2,833 Slices, and 18 Block RAMs in the Xilinx Vertex IV FPGA. In the Modelsim - based simulation result, the proposed hardware accelerator takes 3.06 ms to extract 954 features from a image with $640{\times}480$ pixels and this result shows the cost effectiveness of the propose scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• Journal of the Korea Society of Computer and Information
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• v.16 no.5
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• pp.61-71
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• 2011

To measure the fatigue of metallic objects at high speed vibration while non-contact precision displacement measurement on how to have a lot of research conducted. Noncontact high-speed vibration detection sensor of the eddy current sensors and laser sensors are used, but it is very expensive. Recently, High-speed vibrations detection using an inexpensive inductive sensor to have been studied, but is still a beginner. In this paper, a new design of an inexpensive inductive proximity sensor has been suggested in order to measure high frequency dynamic displacements of metallic specimens in a noncontact manner. Detection of the existing inductive sensors, detection, integral, and amplified through a process to detect the displacement noise due to weak nature of analog circuits and integral factor in the process of displacement detection is slow. The proposed method could be less affected by noise, the analog receive and high-speed signal processing is a new way, because AD converter (Analog to Digital converter) without using the vibration frequency signals directly into digital signals are converted. In order to evaluate the sensing performance, The proposed sensor module using non-contact vibration signals were detected while shaker vibration frequencies from 30Hz to 1,100 Hz at intervals of vibrating metallic specimens. Experimental results, Vibration frequency detection range of the metallic specimins within close proximity to contactless 5mm could be measured from DC to 1,100Hz and vibration amplitude of the resolution was $20{\mu}m$. Therefore, the proposed non-contact inductive sensor module for precision vibration detection sensor is estimated to have sufficient performance.

• Journal of Broadcast Engineering
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• v.10 no.3
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• pp.413-421
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• 2005

As the population of HDTV is growing, among many useful features of modern set top boxes (STBs) or digital video recorders (DVRs), video browsing, visual bookmark, and picture-in-picture capabilities are very frequently required. These features typically employ reduced-size versions of video frames, or thumbnail images. Most thumbnail generation approaches generate DC images directly from a compressed video stream. A discrete cosine transform (DCT) coefficient for which the frequency is zero in both dimensions in a compressed block is called a DC coefficient and is simply used to construct a DC image. If a block has been encoded with field DCT, a few AC coefficients are needed to generate the DC image in addition to a DC coefficient. However, the bit length of a codeword coded with variable length coding (VLC) cannot be determined until the previous VLC codeword has been decoded, thus it is required that all codewords should be fully decoded regardless of their necessary for DC image generation. In this paper, we propose a method especially for fast DC image generation from an I-frame using multiple-symbol lookup table (mLUT). The experimental results show that the method using the mLUT improves the performance greatly by reducing LUT count by 50$\%$.

• Journal of Broadcast Engineering
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• v.24 no.6
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• pp.1076-1084
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• 2019

In this paper, we introduced a system that extracts metadata by recognizing characters and objects in media using deep learning technology. In the field of broadcasting, multimedia contents such as video, audio, image, and text have been converted to digital contents for a long time, but the unconverted resources still remain vast. Building media archives requires a lot of manual work, which is time consuming and costly. Therefore, by implementing a deep learning-based metadata generation system, it is possible to save time and cost in constructing media archives. The whole system consists of four elements: training data generation module, object recognition module, character recognition module, and API server. The deep learning network module and the face recognition module are implemented to recognize characters and objects from the media and describe them as metadata. The training data generation module was designed separately to facilitate the construction of data for training neural network, and the functions of face recognition and object recognition were configured as an API server. We trained the two neural-networks using 1500 persons and 80 kinds of object data and confirmed that the accuracy is 98% in the character test data and 42% in the object data.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.2
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• pp.57-64
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• 2015

At the case of peak threshold algorithm, 3-axes data should sample step data over 20 Hz to get sufficient accuracy. But most of the digital sensors like 3-axes accelerometer have very low sampling rate caused by low data communication speed on limited SPI or $I^2C$ bandwidth of the low-cost MPU for ubiquitous devices. If the data transfer rate of the 3-axes accelerometer is getting slow, the sampling rate also slows down and it finally degrades the data accuracy. In this study, we proved there is a distinct functional relation between the sampling rate and threshold on the peak threshold step detection algorithm under the 20Hz frequency, and made a threshold function through the experiments. As a result of experiments, when we apply threshold value from the threshold function instead of fixed threshold value, the step detection error rate can be lessen about 1.2% or under. Therefore, we can suggest a peak threshold based new step detection algorithm with threshold function and it can enhance the accuracy of step detection and step count. This algorithm not only can be applied on a digital step counter design, but also can be adopted any other low-cost ubiquitous sensor devices subjected on low sampling rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Korean Institute of Traditional Landscape Architecture
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• v.35 no.1
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• pp.68-82
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• 2017

Strengthening surveillance, one of the most important factors in the crime prevention environment of cultural heritages, has difficulty in evaluating and diagnosing the site. For this reasons, surveillance enhancement has been assessed by modelling the shape of cultural heritage, topography, and trees digitally. The purpose of this study is to develop the evaluation method of crime prevention environment for cultural heritage by using the 3D visual exposure index (3DVE) which can quantitatively evaluate the surveillance enhancement in three dimensions. For the study, the evaluation factors were divided into natural, organizational, mechanical, and integrated surveillance. To conduct the analysis, the buildings, terrain, walls, and trees of the study site were modeled in three dimensions and the analysis program was developed by using the Unity 3D. Considering the working area of the person, it is possible to analyze the surveillance point by dividing it into the head and the waist position. In order to verify the feasibility of the 3DVE as the analysis program, we assessed the crime prevention environment by digitally modeling the Donam Seowon(Historic Site No. 383) located in Nonsan. As a result of the study, it was possible to figure out the problems of patrol circulation, the blind spot, and the weak point in natural, mechanical, and organizational surveillance of Donam Seowon. The results of the 3DVE were displayed in 3D drawings, so that the position and object could be identified clearly. Surveillance during the daytime is higher in the order of natural, mechanical, and organizational surveillance, while surveillance during the night is higher in the order of organizational, mechanical, and natural surveillance. The more the position of the work area becomes low, the more it is easy to be shielded, so it is necessary to evaluate the waist position. It is possible to find out and display the blind spot by calculating the surveillance range according to the specification, installation location and height of CCTV. Organizational surveillance, which has been found to be complementary to mechanical surveillance, needs to be analyzed at the vulnerable time when crime might happen. Furthermore, it is note that the analysis of integrated surveillance can be effective in examining security light, CCTV, patrol circulation, and other factors. This study was able to diagnose the crime prevention environment by simulating the actual situation. Based on this study, consecutive researches should be conducted to evaluate and compare alternatives to design the crime prevention environment.