• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.05a
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• pp.186-186
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• 2004

정보화 산업의 급속한 발전을 통하여 무수히 많은 양의 정보들이 디지털화되어 왔고, 이러한 정보를 인식하기 위해서 인간은 멀티미디어나 컴퓨터를 통해 디지털화된 환경에 접속하게 되는데, 이는 시각과 청각을 통해 디지털화된 정보를 인간에게 전달하여 준다 이러한 시각과 청각을 이용한 정보 입출력 장치를 장시간 사용할 경우 정신적으로나 육체적으로 피곤함［l］과 지루함을 느끼게 되고, 장시간 사용이후에도 외부환경에 대한 반응이 일순간 둔감해질 수도 있다.(중략)

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.218-222
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• 2001

본 논문에서는 B-WLL 상향링크 수신기용 심볼 및 위상 동기 회로를 설계하였다. B-WLL 상향링크는 버스트 전송 방식이고, 변조 방식은 QPSK를 사용한다. 본 연구에서는 심볼율을 2.5 Msymbol/sec로 가정하였고, 디지털 Up/Down Converter를 이용한 IF 대역은 20 [MH]를 사용하였다. 수신필터는 25 탭, 7 비트 계수를 가지는 FIR 필터로 설계하였다. 심볼 타이밍 복구 회로는 Gardner 알고리즘을 이용하여 설계하였으며, 반송파 복구는 결정 지향 알고리즘을 이용하여 설계하였다. 설계된 알고리즘은 VHDL로 코딩되어 FPGA에 구현되었다. 실험에 사용된 FPGA는 ALTERA사의 APEX20KE 시리즈의 60만 게이트 FPGA이다. 구현된 복조기의 성능을 평가하기 위하여 모의실험 결과와 구현 결과를 비교하여 제시하였다. 그 결과로 주파수 오프셋과 위상 오프셋이 있는 경우에도 심볼 타이밍 복구 회로는 잘 동작을 하였으며, 주파수 오프셋이 심볼율의 0.12%까지 위상 동기회로가 잘 동작하였다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.122-133
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• 2013

An arbiter-based simple phase decision circuit (PDC) optimized for high-resolution phase-to-digital converter made up of an analog phase-frequency detector and a time-to-digital converter for all-digital phase-locked loops is proposed. It can distinguish very small phase difference between two pulses even though it consumes lower power and has smaller input-to-output delay than the previously reported PDC. Proposed PDC is realized using 130-nm CMOS process and demonstrated by transistor-level simulations. A 5-bit P2D having no offset nor deadzone using the PDC is also demonstrated. A harmonic-lock-free and small-phase-offset delay-locked loop for fixing the P2D resolution regardless of PVT variations is also proposed and demonstrated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.31-38
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• 2009

To improve the image quality and lower the power consumption of the mobile applications, it is the one of the best candidate to control the backlight unit of the LCD module with ambient light. Ambient light sensor and readout circuit were integrated in LCD panel for the mobile applications, and we designed them with LTPS TFT. We proposed noble start-up correction in order to correct the variation of the photo sensors in each panel. We used time-to-digital method for converting photo current to digital data. To effectively merge time-to-digital method with start-up correction, we proposed noble dual slope correction method. The entire readout circuit was designed and estimated with LTPS TFT process. The readout circuit has very simple and stable structure and timing, so it is suitable for LTPS TFT process. The readout circuit can correct the variation of the photo sensors without an additional equipment, and it outputs the 4-levels digital data per decade for input luminance that has a dynamic range of 60dB. The readout rate is 100 times/sec, and the linearity error for digital conversion is less than 18%.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1218-1219
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• 2011

본 논문은 KA555 Timer을 이용한 PWM회로로 구성된 아날로그 방식의 DC-DC Buck Converter와 AVR ATmega128를 이용한 PWM회로로 구성된 디지털 방식의 Buck Converter을 설계하여 각각의 특성을 비교 분석하였다. 제안된 컨버터들은 공통적으로 전원을 공급받아 전압분압회로를 통해 DC-DC Buck Converter의 PWM 제어회로부에 공급되며, 아날로그방식 컨버터의 제어부는 KA555 timer을 이용하여 구형파회로와 미분회로를 구성하고, 출력된 삼각파와 정현파를 KA555 timer을 이용하여 PWM파형으로 제어한다. 디지털방식의 컨버터는 AVR RISC 8-bit 마이크로프로세서 ATmega128을 이용하여 PWM 제어부를 구성하고 이를 LCD창을 통해 그 값을 확인할 수 있도록 설계하였다. 본 논문에서는 두 가지 방식의 제어부를 구성하여 제작 및 실험함으로써, 각각의 장단점을 비교하여 시스템 구성시 요구조건인 소형경량, 단가저감, 효율 등을 비교하여 그 상황에 맞는 설계가 가능할 것이다.

• Journal of Digital Contents Society
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• v.13 no.3
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• pp.413-420
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• 2012

In this paper, PBL-based design education(PBDE) techniques for effective engineering design education to assess the infrastructure and outcome of creative engineering education which has been recognized as an important target in accreditation system of engineering education and a case of contents development as PBDE application to the logic circuit design that is essential integrant course of IT division of universities is presented. Because integrant design is based on compositional technologies with restricted realistic constraints, design components and the application of realistic constraints are different from those of capstone design. PBL technique must be carefully considered as it is used for creative design education. We applied the developed content to real design classes for validation of its performance and effectiveness.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.34-41
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• 2011

This paper presents a 24 channel capacitive touch sensing ASIC. This ASIC consists of analog circuit part and digital circuit part. Analog circuits convert user screen touch into electrical signal and digital circuits represent this signal change as digital data. Digital circuit also has an I2C interface for operation parameter reconfiguration from host machine. This interface guarantees the stable operation of the ASIC even against wide operation condition change. This chip is implemented with 0.18 um CMOS process. Its area is about 3 $mm^2$ and power consumption is 5.3mW. A number of EDA tools from Cadence and Synopsys are used for chip design.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.9
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• pp.855-860
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• 2016

This study describes the design and implementation of digital Payload power supply. We materialized the interface of the PLDIU and power supply of a satellite bus, and minimized the potential for the occurrence of such erroneous operation circuit ESD through the WCA of the space environment. We designed a reliable power supply through simulation for a TID according to the vibration generated during the launch and space radiation environment, and found no problem in the function and performance through the test space environment after production.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.5
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• pp.478-486
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• 2000

This paper proposes a design method that can minimize the power dissipation of CMOS digital circuits without affecting their optimal operation speeds. The proposed method is based on genetic algorithms(GAs) combined to the retiming technique, a circuit transformation technique of repositioning flip-flops. The proposed design method consists of two phases: the phase of retiming for optimizing clock periods and the phase of GA retiming for minimizing power dissipation. Experimental results using Synopsys Design Analyzer show that the proposed design method can reduce the critical path delay of example circuits by about 30-50% and improve the dynamic power performance of the circuits by about 1.4~18.4%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1884-1891
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• 2012

In this paper, we design the sliding correlator SS transceiver which supports short message service. We also analyze the PN code acquisition circuit that is essential for spread spectrum receiver. Using Maxplus II tool provided by altera Co., Ltd, we have designed PN code generator, and sliding correlator for PN code acquisition. Then, they have been made into FPGA by way of EPM7064SLC44-10 - a chip of Altera Co., Ltd. Additionally, we have designed delay clock circuit which is faster than the clock of Tx PN clock, designed switching circuit to control the clock rate and data demodulation circuit. The performance of the transceiver is evaluated from the experimental results. Especially, the performance of PN code acquisition accomplished by sliding correlator which is very important to evaluate spread spectrum receiver is evaluated with the comparison of the lock states.