• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.326-332
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• 1996

In this paper, a method to design the sending loudness rating(SLR) is proposed and the desirable transmission characteristics are considered in order to specify the transmission quality, based on the loudness ratings, for the digital telephone system that is a terminal for digital speech communication. To specify the desirable SLR for digital telephone system, the subjective test defining the preferred range of inout level for CODEC was performed. From the test results, it was identified that the optimal input level for CODEC is -15dB and the range not to cause the quantization noise and the distortion of CODEC fall within -12dB and -18dB.

• Journal of Broadcast Engineering
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• v.6 no.1
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• pp.66-71
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• 2001

This paper Introduces an implementation of MPEG-2 AAC codec system for digital audio broadcasting. This system consists of the encoder and the decoder. This system includes MPEG-2 system multiplexing and demultiplexing modules for Interfacing to the ETRI-DAB system. Four DSPs are adopted for the encoder and three DSPs for 7he decoder. Each DSP Processes system control. 1/0 control, audio signal processing. multiplexing and demultiplexing. This Paper also discusses some near future estimations relaxed to the DAB system and it\`s services. Currently a stereo audio codec is available but multi-channel audio codec and MPEG-4 audio cosec wall be also Implemented.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1990.06a
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• pp.448-450
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• 1990

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.360-367
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• 2006

In this paper, we designed a digital codec of an RFID tag for EPC global generation 2 class 1. There are a large number of studies on RRD standard and anti-collision algorithm but few studies on the design of digital parts of the RFID tag itself. For this reason, we studied and designed the digital codec hardware for EPC global generation 2 class 1 tag. The purpose of this paper is not to improve former studies but to present the hardware architecture, an estimation of hardware size and power consumption of digital part of the RFID tag. Results are synthesized using Synopsys with a 0.35um standard cell library. The hardware size is estimated to be 111640 equivalent inverters and dynamic power is estimated to be 10.4uW. It can be improved through full-custom design, but we designed using a standard cell library because it is faster and more efficient in the verification and the estimation of the design.

• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.61-68
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• 2008

In this paper, we propose the VLSI design of Multi-Format Video Decoder (MFD) to support video codec standards such as MPEG-2, MPEG-4, H.264 and VC-1. The target of the proposed MFD is the Full HD (High Definition) video processing needed for the high-end D-TV SoC (System-on-Chip). The size of the design is reduced by sharing the common large-size resources such as the RISC processor and the on-chip memory among the different codecs. In addition, a detachable architecture is introduced in order to easily add or remove the codecs. The detachable architecture preserves the stability of the previously designed and verified codecs. The size of the design is about 2.4 M gates and the operating clock frequency is 225MHz in the Samsung 65nm process. The proposed MFD supports more than Full-HD (1080p@30fps) video decoding, and the largest number of video codec standards known so far.

• Journal of Internet Computing and Services
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• v.11 no.4
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• pp.23-32
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• 2010

In this paper, we first propose the security enhancing of authentication protocol for Hash based RFID tag, and then a digital Codec for RFID tag is designed based on the proposed authentication protocol. The protocol is based on a three-way challenge response authentication protocol between the tags and a back-end server. In order to realize a secure cryptographic authentication mechanism, we modify three types of the protocol packets which defined in the ISO/IEC 18000-3 standard. Thus active attacks such as the Man-in-the-middle and Replay attacks can be easily protected. In order to verify effectiveness of the proposed protocol, a digital Codec for RFID tag is designed using Verilog HDL, and also synthesized using Synopsys Design Compiler with Hynix $0.25\;{\mu}m$ standard-cell library. Through security analysis and comparison result, we will show that the proposed scheme has better performance in user data confidentiality, tag anonymity, Man-in-the-middle attack prevention, replay attack, forgery resistance and location tracking.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10A
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• pp.1015-1022
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• 2007

In this paper, dual-band digital codec for UHF(Ultra High Frequency) and MW(Micro Wave) is proposed for an RFID reader system. Most RFID systems have been supported only one protocol. But, There are many protocols of each bandwidth. Especially, UHF bandwidth which is widely used on the globe consists of A,B,C type, and more standards will be established. Recently, Since an interest about mobile RFID system is increasing, the RFID system with more than one protocol will be need. Therefore, this paper suggests a dual-band digital codec with UHF and MW bands for an RFID reader system. Standards used in this system are 18000-6C and 18000-4 standards. The digital codec is synthesize by the Quartus II compiler. Target device is EPC20Q240C8 which is family of CycloneII. Main Clock is 19.2MHz and elements of FPGA which is used for the system is 18,752.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2000.11b
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• pp.43-48
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• 2000

This paper introduces MPEG-2 AAC codec system fur digital audio broadcasting. This system consists of encoder and decoder, and this system provides MPEG-2 system multiplexing and demultiplexing functions. Four DSPs are adopted fur encoder and three DSPs fur decoder. Each DSP processes system control, I/O control, and audio signal processing, multiplexing and demultiplexing. This paper also discusses about some near future estimations related to DAB system and services. And at the end of this paper describes about future development plans.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1983.10a
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• pp.77-80
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• 1983

90Mbps 디지털 비데오 코덱의 구성방법으로 서pel 당 비트수, sampling 주파수, 데이터 감축 방법등의 여러가지 설계 요건들이 SQNR, 하아드웨어 복잡성 정도에 따라 비교검토 되었으며 그 결과 HBL control을 포함하는 9bit PCM codec 방식이 90Mbps 전송속도에서 타당함이 밝혀졌다.

• Journal of Broadcast Engineering
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• v.2 no.1
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• pp.24-35
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• 1997

Basic and transmission video quality testing was performed in real-time mode using hardware video codec based on MPEG-2 MP@ML standard including subsequent transmitting and receiving satellite simulator unit. The double-stimulus Impairment scale method and the double-stimulus continous quality scale method based on CCIR 500-5 were used as an evaluation method. The whole digital broadcasting satellite system consisting of MPEG-2 codec, system mux/demux, channel codec, channel, modem, antenna, etc. was put into the overall video quality testbed and the basic and transmission error quality assessment was performed at various bitrates and BER for an integrated system performance evaluation. In transmission error video quality testing, transmission error video quality maintained on average above 3.9 point on the 5-point scale. The low-bit rate quality such as film mode(@2Mbps) highly depended on the statitical characteristics of video source and maintained on average around 2.7 point.