• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.16 no.6
• /
• pp.454-464
• /
• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.

• 한국HCI학회:학술대회논문집
• /
• 2006.02c
• /
• pp.854-858
• /
• 2006

디지털화의 가속, 고속 통신 인프라의 확대 등으로 전자, 정보 통신 기기들이 단일 네트워크로 연결되어 영상 및 음향 정보를 서로 공유할 수 있으며, 생활 공간 내에서 실생활의 질 향상을 위한 지능적 정보 서비스와 자연스럽고 편한 내추럴 인터페이스 기술에 의한 지능형 반응 정보 서비스 공간 기술이 중요한 이슈로 등장하고 있다. 본 연구에서는 지능형 반응 공간의 물리적 객체로서 학교, 연구 기관 및 회사 등의 회의실을 선정한다. 그리고, 이를 대상으로 회의 참여자들이 자연스럽고 편리하게 의견 교환, 관련 자료 및 정보 처리를 할 수 있는 시스템 구축을 위한 아키텍처에 대하여 논의한다. 본 연구에서 제안하는 시스템 아키텍처는 회의와 관련된 문서나 회의 내용 등의 정보를 실감 가시화 노드로 추상화되고 메타 정보화함으로써 전체 회의 내용의 파악과 회의 정보에 대한 체계적이고 논리적인 관리를 가능하게 한다. 또한 여러 사람의 공동 작업을 필요로 하는 정보 또는 문서에 대한 동시 편집 기능과 자연스러운 동작에 의한 데이터 조작을 지원하는 실감 워크벤치 및 워크스크린 기술, 정보 핸들링의 다양성과 조작의 편리성을 위한 실감 아이콘에 의하여 자연스럽고 편리한 회의를 가능하게 한다. 그리고, 이러한 요소 기술들이 에이전트에 의해 회의 프로세스 및 요소 기술들의 시스템적 통합을 가능하게 한다.

• Journal of KIISE:Software and Applications
• /
• v.35 no.3
• /
• pp.149-161
• /
• 2008

As Programmable Logic Controllers(PLCs) are frequently used to implement real-time safety critical software, testing of PLC software is getting more important. We propose a structural testing technique on Function Block Diagram(FBD) which is one of the PLC programming languages. In order to test FBD networks, we define templates for function blocks including timer function blocks and propose an algorithm based on the templates to transform a unit FBD into a flowgraph. We generate test cases by applying existing testing techniques to the generated flowgraph. While the existing FBD testing technique do not consider infernal structure of FBD to generate test cases and can be applied only to FBD from which the specific intermediate model can be generated, this approach has advantages of systematic test case generation considering infernal structure of FBD and applicability to any FBD without regard to its intermediate format. Especially, the proposed method enables FBD networks including timer function blocks to be tested thoroughly. To demonstrate the effectiveness of the proposed method, we use trip logic of bistable processor of digital nuclear power plant protection systems which is being developed in Korea.

• 전자공학회논문지 IE
• /
• v.46 no.4
• /
• pp.1-7
• /
• 2009

The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.1
• /
• pp.47-56
• /
• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.6
• /
• pp.131-137
• /
• 2013

The barrel distortion makes serious problems in a wide-angle camera employing a lens of a short focal length. This paper presents a low-complexity hardware architecture for a real-time barrel distortion corrector and its implementation. In the proposed barrel distortion corrector, the conventional algorithm is modified so that the correction is performed incrementally, which results in the reduction of the number of required hardware modules for the distortion correction. The proposed barrel distortion corrector has a pipelined architecture so as to achieve a high-throughput correction. The correction rate is 74.86 frames per sec at the operating frequency of 314MHz in a $0.11{\mu}m$ CMOS process, where the frame size is $2048{\times}2048$. The proposed barrel distortion corrector is implemented with 14.3K logic gates.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.42 no.3 s.303
• /
• pp.63-70
• /
• 2005

The electrodeless lamps using the induction discharge have a long lifetime and a high tolerance for the variable output conditions of a ballast since they don't need the electrodes. This paper proposed two novel dimming algorithms for the Electrodeless lamps and described the resonant inverter adopted the proposed methods. The proposed dimming algorithms are based on the conventional burst dimming method which is normally adopted for LCD back-lights. One of the proposed algorithms is a improved burst dimming method, which controls the illumination by duty ratio of $5\%$ and its control circuit is formed by simple digital logics. The other algorithm is a burst PWM average duty ratio control method, which controls the illumination by duty ratio of $1\%$ and its control circuit is formed by more complex digital logics than the first method. To verify the validity of the proposed dimming methods, a prototype experimental setup for 100W Electrodeless lamps is carried out and its results are presented in this paper.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.8
• /
• pp.1464-1474
• /
• 1994

GPS(Global Positioning System)is a satellite-based navigation system that we can survey where we are, anywhere and anytime. In this paper, delay-lock loop of the receiver which detects the navigation data is theoretically analyzed, and designed using the digital logic circuit. Also logic operations for the synchronization are analyzed. The designed system consists of the correlator which correlates the received C/A code and the generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock syntheizer which generates the clock of the C/A code generator to control the C/A code phase and clock rate. From the analyses results of the proposed digital delay-lock loop system, the system has the detection propertied over 90% when its input signal power is above-113.98dB. The influence of input signal variation of digital delay loop, which is the input of A/D converter, is investigated and the performance is analyzed with the variation of threshold level via the computer simulation. The logic simulation results show that the designed system detects precisely the GPS navigation data.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.9
• /
• pp.1-10
• /
• 1998

This paper is to propose an algorithm named as DYSAC to find the critical path(the longest sensitizable path) in a large digital circuit, whose purpose is to reduce the time to find critical path and to find critical paths of the circuits for which the previous methods could not find one. Also a set of path sensitization criteria named as DYPSEC is proposed, which is used to select a path from input to the output inside the DYSAC. The DYSAC consists of two sub-algorithms; the level assignment algorithm to assign a level to each node and the critical path selection algorithm to select the sensitizable path. The proposed algorithm was implemented with C-language on SUN Sparc and applied to the ISCAS'85 benchmark circuits to make sure if it works correctly and finds the correct critical path. Also, the results from the experiments were compared to the results from the previous works. The comparison items were the ability to find the critical path and the speed, in both of which the proposed algorithm in this paper shows better results than others.

• The Korean Journal of Archival Studies
• /
• no.79
• /
• pp.5-32
• /
• 2024

The Korean government ranked 3rd among 193 UN member countries in the UN's 2022 e-Government Development Index. Korea, which has consistently been evaluated as a top country, can clearly be said to be a leading country in the world of e-government. The lubricant of e-government is data. Data itself is neither information nor a record, but it is a source of information and records and a resource of knowledge. Since administrative actions through electronic systems have become widespread, the production and technology of data-based records have naturally expanded and evolved. Technology may seem value-neutral, but in fact, technology itself reflects a specific worldview. The digital order of new technologies, armed with hyper-connectivity and super-intelligence, not only has a profound influence on traditional power structures, but also has an a similar influence on existing information and knowledge transmission media. Moreover, new technologies and media, including data-based generative artificial intelligence, are by far the hot topic. It can be seen that the all-round growth and spread of digital technology has led to the augmentation of human capabilities and the outsourcing of thinking. This also involves a variety of problems, ranging from deep fakes and other fake images, auto profiling, AI lies hallucination that creates them as if they were real, and copyright infringement of machine learning data. Moreover, radical connectivity capabilities enable the instantaneous sharing of vast amounts of data and rely on the technological unconscious to generate actions without awareness. Another irony of the digital world and online network, which is based on immaterial distribution and logical existence, is that access and contact can only be made through physical tools. Digital information is a logical object, but digital resources cannot be read or utilized without some type of device to relay it. In that respect, machines in today's technological society have gone beyond the level of simple assistance, and there are points at which it is difficult to say that the entry of machines into human society is a natural change pattern due to advanced technological development. This is because perspectives on machines will change over time. Important is the social and cultural implications of changes in the way records are produced as a result of communication and actions through machines. Even in the archive field, what problems will a data-based archive society face due to technological changes toward a hyper-intelligence and hyper-connected society, and who will prove the continuous activity of records and data and what will be the main drivers of media change? It is time to research whether this will happen. This study began with the need to recognize that archives are not only records that are the result of actions, but also data as strategic assets. Through this, author considered how to expand traditional boundaries and achieves reterritorialization in a data-driven society.