• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.293-298
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• 1999

본 논문은 수중음의 안정적 실시간 인식을 위한 새로운 음원 인식 알고리즘을 다루고 있다 본 논문에서 이용된 주파수인식 알고리즘은 크게 네 부분으로 구성되어 있는데 1)입력된 음파 신호를 duty cycle $50\%$의 디지털 신호로 바꾸고 기준 주파수의 음원을 duty cycle $50\%$, 위상차 0도 90도 180도 270도의 디지털 신호를 생성하는 부분, 2)입력된 음파신호를 4가지 위상의 각 기준신호와 배타적 논리합을 구하는 부분, 3)두 번째에서 만들어진 각 신호를 적분회로에 통과시키는 부분, 4)세 번째에서 발생한 각 신호중 최대값을 추출하여 입력된 음파신호의 주파수를 인식하는 부분으로 이루어져 있다. 이 회로에 대한 수치 해석을 통하여 각 부분의 특성치에 대한 최적 값 및 성능을 검증하였으며, 이의 결과를 각각 computer 수치 시험, 실제 회로 실험과 비교하였다.

• Journal of Advanced Navigation Technology
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• v.24 no.4
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• pp.314-321
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• 2020

Logic automated stimulus and response (LASAR) software is an automatic test program development tool for logic function test and fault detection of avionics components digital circuit cards. LASAR software needs to the information for the logic circuit function and input and output of the device. If there is no component information, normal component modeling is impossible. In this paper, component modeling is carried out through reverse design of programmable logic device (PLD) device without element information. The developed LASAR program identified failure detection rates through fault simulation results and single-seated fault insertion methods. Fault detection rates have risen by 3% to 91% for existing limited modeling and 94% for modeling through the reverse design. Also, the 22 case of stuck fault with the I/O pin of EP310 PLD were detected 100% to confirm the good performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.1
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• pp.26-30
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• 2012

In this paper, we propose a signal generation method of rectangular QAM for rotationally invariant I/Q TCM. The proposed method consists of only digital logic gates without look-up table so that we can implement the system compactly. Our scheme can be applied to every rectangular QAM with the level higher than 64.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.111-113
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• 2007

본 논문에서는 FPGA를 사용하여 진행파형 초음파 모 터의 2상 입력 전원 전압의 주파수, 위상차, 진폭 및 2 상간의 전압차 조절이 가능하고, 8대의 초음파 모터를 동 시에 제어할 수 있는 8채널 USB통신 PC기반 초음파 모터 디지털 제어기를 제안한다. 제안한 제어기는 FPGA를 이용 한 디지털 논리에 의해 출력을 발생하기 때문에 PC로부 터 직접 제어 명령을 입력 받아 각각의 파라미터를 실시 간으로 조절할 수 있을 뿐만 아니라, 둘 이상의 파라미터 를 동시에 조절이 가능하다. 또한, PC와의 인터페이스는 USB통신 방식을 채택하여 제어 명령의 전달속도 향상 및 플러그 앤 플러그 방식을 통해 데스크 탑 컴퓨터는 물론 휴대용 컴퓨터나 PDA와 같은 다양한 플랫폼에서 사용할 수 있도록 설계하였다. 또한, 초음파 모터의 속도 및 위치를 계측하기 위해 사용된 로터리 엔코더 카운터 회로를 FPGA회로에 내장시켜 카운터를 위한 별도의 회로 구성이나 장비 구입의 필요성을 배제하였다. 따라서, 생산 단가 및 부피를 현저히 감소시켰다.

• KIISE Transactions on Computing Practices
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• v.23 no.6
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• pp.335-342
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• 2017

In the verification and validation procedures regarding the safety-critical software of nuclear power plants for the attainment of the requisite license from the regulatory body, it is difficult to judge the safety and dependability of the development, implementation, and validation activities through a simple reading and review of the documentation. Therefore, these activities, especially safety assurance activities, require systematic evaluation techniques to determine that software faults are acceptable level. In this study, a safety case methodology is applied in an assessment of the level and depth of the results of the development and validation of a manufacturer in its targeting of the bistable processor of a digital reactor protection system, and the evaluation results are analyzed. This study confirms the possibility of an effective supplementation of the existing safety demonstration method through the application of the employed safety case methodology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2064-2071
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• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.70-78
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• 2000

A novel capacitance deviation-to-time interval converter based on ramp-integration is presented. It consists of two current mirrors, two schmitt triggers, and control digital circuits by the upper and lower sides, symmetrically. Total circuit has been with discrete components. The results show that the proposed converter has a linearity error of less than 1% at the time interval(pulse width) over a capacitance deviation from 295 pF to 375 pF. A capacitance deviation of 40pF and time interval of 0.2 ms was measured for sensor capacitance of 335 pF. Therefore, the high-resolution can be known by counting the fast and stable clock pulses gated into a counter for time interval. The application of a novel capacitance deviation-to time interval converter to a digital humidity controller is also presented. The presented circuit is insensitive to the capacitance difference in disregard of voltage source or temperature deviation. Besides the accuracy, it features the small MOS device count integrable onto a small chip area. The circuit is thus particularly suitable for the on-chip interface.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.2
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• pp.219-230
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• 2002

One of the most important functions digital libraries need to offer is to help users find necessary information in a distributed environment in the most efficient and effective manner. In order to meet the goal, it is desirable to link scattered pieces of information and present them as a logically coherent whole when the user wants it, so that he or she doesn't need to know their physical location. The virtual document is an integrated document that the total or part of the physical documents stored in a specific repository are linked dynamically. Our MIRAGE-III digital library system provides a content-based retrieval of physical documents and the virtual documents in XML. This system provides a retrieval of partial documents, attributes and hierarchical structures and linked-documents based in structured documents like XML or SGML. In this paper we describe a methodology of design and implementation of the query processor and retrieval server in the MIRAGE-III digital library system.

• 대한공업교육학회지
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• v.33 no.1
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• pp.149-168
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• 2008

The purpose of this study is to verify the effect of PSpice instruction on academic achievement in 'Combination logic circuit' unit of 'Digital Logic Circuit' in industrial high school. Three kinds of null hypotheses were formulated. Two classes of the third grade of C technical high school in Gyeong-buk were divided into experimental group and control group in order to verify null hypotheses. In the experimental design, 'Non-equivalent control group pretest-posttest' model was utilized. This experiment was conducted for six classes, the experimental group was applied to PSpice instruction method before the circuit traning while the control group was applied to traditional lecture oriented method before the circuit traning. Window SPSS 10.0 korean language version program was used for the data analysis and independent sample t-test was used to identify the average of each group. Significance level was set to .05 level. The results obtained in this study were as follows; First, PSpice instruction had not an effect on academic achievement according to a group type. However, these instruction had an effect on the following sub-domains; the psychomotor domain. Second, PSpice instruction had not an effect on academic achievement according to a studies level. However, these instruction for middle and low level students had an effect on the cognitive and psychomotor domain, and for middle level students had an effect on the affective domain. Third, PSpice instruction had not an effect on shortening of a training requirement. However, this instruction for low level students had an effect on shortening of a training requirement. The study results of simulation instruction was chiefly efficient in the psychomotor domain. We could know that simulation instruction is efficient as went to a low level students than an upper level students. Thus, We may make the study effectiveness in various instruction method.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.5
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• pp.231-236
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• 2008

This paper proposes a cost-efficient and flexible FPGA-based logic circuit emulation platform. By improving the performance and adding more features, this new platform is an enhanced version of our LAPG. It consists of an FPGA-based hardware engine and software element to drive the emulation and monitor the results. It also provides an interactive verification environment which uses an efficient communication protocol through a bi-directional serial link between the host and the FPGA board. The experimental results show that this new approach saves $55%{\sim}99%$ of communication overhead compared with other methods. According to the test results, the new LAPG is more area efficient in complex circuits with many I/O ports.