• Journal of the Korea Society of Computer and Information
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• v.18 no.5
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• pp.9-17
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• 2013

This paper presents the design of the educational router system. This system is designed and implemented to support network configuration and embedded programming technology of the user on Internet. Not only Static routing protocol but also a kind of dynamic routing protocols such as OSPF and RIP and firewall have been programmed for education based on ethernet interface. ADS 1.2 as debugging environment, uC/OS-ii as RTOS and C language as development language are used. The educational procedures is compile, loading of static routing protocol, a kind of dynamic routing protocols such as OSPF and RIP and firewall program already supplied. Thereafter the verification is checked by using "ping" test to allow for demo operation such as hands-on training procedure. Finally programming procedure similar with demo operation of static routing protocol, a kind of dynamic routing protocols such as OSPF and RIP and packet filtering function is educated step by step.

• Aerospace Engineering and Technology
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• v.10 no.2
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• pp.105-113
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• 2011

During the development of flight software, the processor emulator and satellite simulator are essential tools for software development and verification, which can be substituted for the actual hardware. LEO satellites being developed by KARI recently use the MCM-ERC32SC processor for on-board computer (OBC). For the flight software (FSW) development and testing, the software-based spacecraft simulator was developed using TSIM-ERC32 processor emulator from Aeroflex Gaisler. It is needed to get rid of the constraints and dependencies of TSIM-ERC32 processor emulator and to obtain high performance processor emulator to develop full satellite simulator. This paper presents the development of the ERC32 emulator based on open source dynamic translator, QEMU, as the first step. And it describes the software development and testing/debugging on the developed emulator.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.436-439
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• 2005

As mobile computers and embedded systems are becoming popular recently, we need to study how to utilize the resources such as power, space, CPU clocks, and memory efficiently. In traditional embedded system development, we were interested in resource usage based on hardware but, as software is becoming more important, we need to study how to analyze the resource usage based on software. In this research, we propose a new method called 'Instruction Level Resource Usage Analysis Method' and implement it as a resource usage analysis tool called 'I-Debugger'. I-Debugger is constructed on three layers: debugging layer which controls the execution of software on instruction level, statistic layer which gathers real-time data and convert to useful information, and analysis layer which generate useful information to specific applications. We have applied the debugger to some simple problem and found that our method is useful in developing resource efficient embedded systems.

• The KIPS Transactions:PartA
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• v.18A no.2
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• pp.61-68
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• 2011

Memory error debugging is one of the most critical processes in improving software quality. However, due to the extensive time consumed to debug, the enhancement often leads to a huge bottle neck in the development process of mobile devices. Most of the existing memory error detection tools are based on static error detection; however, the tools cannot be used in mobile devices due to their use of large working memory. Therefore, it is challenging for mobile device vendors to deliver high quality mobile devices to the market in time. In this paper, we introduce "PinMemcheck", a pin-based memory error detection tool, which detects all potential memory errors within $1.5{\times}$ execution time overhead compared with that of a baseline configuration by applying the Pin's binary instrumentation process and a simple data structure.

• The KIPS Transactions:PartA
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• v.11A no.5
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• pp.319-324
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• 2004

The Java language is rapidly being adopted in the Internet. The distributed applications and their application range are being expanded beyond just a programing language and developed Into software applications. A variety of researches are going on with regard to the Java Virtual Machine runtime environment and methods of analyzing the Java class files and utilizing the information for applications. A class file is a converted file that is executable by the Java virtual machine. Analysis on the class file structure and the runtime processes will be convenient in arranging the decompilers and debugging the source programs. This paper is about the runtime process analyzer that presents the runtime processes, including class files, more visually. The content of a class file will be easily accessed and expressed as in a graphic user interface. The information in the class file displayed is divided into Constant_Pool, Class_file, Interface, Field, Method and Attribute with information on method area, operand stack and local variables expressed visually.

• Journal of Satellite, Information and Communications
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• v.7 no.2
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• pp.80-86
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• 2012

The software-based satellite simulator has been developed from the start of the project to resolve the restriction and limitation of using hardware-based software development platform. It enables the development of flight software to be performed continuously since initial phase. The satellite simulator emulates the on-board computer, I/O modules, electronics and payloads, and it can be easily adapted and changed on hardware configuration change. It supports the debugging and test facilities for software engineers to develop flight software. Also the flight software can be loaded without any modification and can be executed as faster than real-time. This paper presents the architecture and design of software-based GEO satellite simulator which has hot-standby redundancy mechanism, and flight software development and test under this environment.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.27 no.6
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• pp.1331-1345
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• 2017

Binary instrumentation has been developed for monitoring and debugging executables without their source codes. Previous efforts on the binary instrumentation are mainly focused on its capability and accuracy, but not on efficiency for practical application. In particular, criteria and measurement methodologies for evaluating and comparing the efficiency of binary investigation tools and algorithms do not estimated yet. In this paper, we propose the instrumentation primitives which are a unit functionality and measurement methodology. Through the empirical experiments by adopting the proposed methodology on DynamoRIO and Pin, we show the feasibility of the proposal.

• KIISE Transactions on Computing Practices
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• v.21 no.8
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• pp.513-523
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• 2015

A complex event processing system, becoming useful in real life domains, efficiently processes stream of continuous events like sensor data from IoT systems. However, those systems do not work well on some types of queries yet, so that programmers should be careful about that. For instance, they do not sufficiently provide detailed guide to choose efficient queries among the almost same meaning queries. In this paper, we propose an query preprocessing tool for event stream processing systems, which helps programmers by giving them the hints to improve performance whenever their queries fall in any possible bad formats in the performance sense. We expect that our proposed module would be a big help to increases productivity of writing programs where debugging, testing, and performance tuning are not straightforward.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.525-534
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• 2002

Race conditions, races in short, need to be detected for debugging parallel programs, because the races result in unintended non-deterministic executions. To detect the races in an execution of program, previous techniques use a centralized data structure which may incur serious bottleneck in generating concurrency information, or show inefficient time complexity which depends on the degree of nested parallelism in comparing any two of them. We propose a new labeling scheme in this paper, which is scalable in generating the concurrency information without bottleneck by using private data structure, and improves time complexity into constant in checking concurrency. The scalability and time efficiency therfore makes on-the-fly race detection efficient not only for programs with either shared-memory or message-passing, but also for programs with mixed model of the two.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.2
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• pp.31-42
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• 2014

Debugger systems are necessary to apply dynamic program analysis when evaluating security properties of embedded system software. It may be possible to make the use of software-based debugger and/or DBI framework if target devices support general purpose operating systems, however, constraints on applicability as well as environmental transparency might be incurred thereby hindering overall analyzability. Analysis with JTAG (IEEE 1149.1) debugging devices can overcome these difficulties in that no change would be involved in terms of internal software environment. In that sense, JTAG API can facilitate to practically perform dynamic program analysis for evaluating security properties of target device software. In this paper, we introduce an implementation of JTAG API to enable analysis of ARM core based embedded systems. The API function set includes the categories of debugger and target device controls: debugging environment and operation. To verify API applicability, we also provide example analysis tool implementations: our JTAG API could be used to build kernel function fuzzing and live memory forensics modules.