• Polymer(Korea)
• /
• v.35 no.4
• /
• pp.356-362
• /
• 2011

The branched polycarbonates (B-PCs) with two different branching agents were synthesized from melt polymerization. The contents of branching agent were in the range of 0.001~0.005 mol%. The chemical structure of the synthesized PC was determined by FTIR, $^1H$ NMR, and $^{13}C$ NMR, spectroscopy. The molecular weight, glass transition and degradation temperatures were determined by GPC, DSC, and TGA. The molecular weight of the phloro type B-PC had a lower value than the other one, and the glass transition temperature increased with molecular weight. Compared with linear PC, the rheological properties of the B-PC indicated an increase of complex viscosity in the low frequency region and shear thinning tendency. Power law index(n) representing shear thinning was calculated by linear regression and the values were in the range of 0.483~0.996. The rheological properties of the B-PCs were measured by a dynamic rheometer.

• Journal of the Korea Society of Computer and Information
• /
• v.14 no.1
• /
• pp.145-151
• /
• 2009

There are excessively hot units of a microprocessor in today's nano-scale process technology, which are called hotspots. Hotspots' heat dissipation is not perfectly conquered by mechanical cooling techniques such as heatsink, heat spreader, and fans; Hence, an architecture-level temperature simulation of microprocessors is evident experiment so that designers can make reliable chips in high temperature environments. However, conventional thermal simulators cannot be used in temperature evaluation of real machine, since they are too slow, or too coarse-grained to estimate overall system models. This paper proposes methodology of monitoring accurate runtime temperature with Hotspot[4], and introduces its implementation. With this tool, it is available to track runtime thermal behavior of a microprocessor at architecture-level. Therefore, Dynamic Thermal Management such as Dynamic Voltage and Frequency Scaling technique can be verified in the real system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.6
• /
• pp.573-582
• /
• 2010

In this paper, X-band transceiver for high resolution wideband SAR systems is designed and fabricated. Also as a technique for enhancing the performance, error compensation algorithm is presented. The transceiver for SAR system is composed of transmitter, receiver, switch matrix and frequency generator. The receiver especially has 2 channel mono-pulse structure for ground moving target indication. The transceiver is able to provide the deramping signal for high resolution mode and select the receive bandwidth for receiving according to the operation mode. The transceiver had over 300 MHz bandwidth in X-band and 13.3 dBm output power which is appropriate to drive the T/R module. The receiver gain and noise figure was 39 dB and 3.96 dB respectively. The receive dynamic range was 30 dB and amplitude imbalance and phase imbalance of I/Q channel was ${\pm}$0.38 dBm and ${\pm}$3.47 degree respectively. The transceiver meets the required electrical performances through the individual tests. This paper shows the pulse error term depending on SAR performance was analyzed and range IRF was enhanced by applying the compensation technique.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
• /
• 1993.04a
• /
• pp.86-92
• /
• 1993

자동차의 현가장치에 대한 능동제어연구는 국내외적으로 활발히 진행되어 왔다. 수동식현가장치는 단순히 스프링과 감쇠기로 차체의 진동을 수동 제어 하므로 성능 향상에 한계가 존재하게 된다. 수동식 현가장치가 강성계수와 감쇠계수를 조절함으로써 차체로 들어오는 진동을 억제하는 반면, 능동식제 어는 보통 유압을 이용하여 효율적으로 차체에 들어오는 진동을 억제시키게 된다. 일반적으로 자동차가 능동현가장치 설계시 요구되는 사항은 탑승자의 승차감, 조종성, 현가장치의 공간확보 문제, 경제성(제어력), 실제적으로 자동 차에 적용할 수 있는 능동제어기법인가 하는 문제이다. 자동차 능동식 현가 장치는 보통 1/4 car (2자유도계), Full-car 모델 (7자유도계) 등으로 모델링 을 하여 능동제어기를 설계한다. 1/4 car 모델의 특징은 해석이 비교적 단순 하고 현가장치의 동적거동을 이해하는데 유용하고 실험을 하거나 실제 자동 차에 적용하기 쉬운 반면에 Full-car 모델에 비해 제어력의 효율이 떨어진다 는 단점이 있다. 그 이유는 1/4 car 모델은 차체의 동역학적 특성을 고려하 여 설계하지 않았기 때문에 4개의 독립현가차축에서는 오직 그 현가축방향 으로 발생하는 수직방향의 진동만을 제어하기 때문이다. 따라서 동역학적 역 성에 기인하는 운동을 제어하는 비효율적인 제어력이 공급된다는 단점을 갖 는다. 이에 비해 full-car 모델은 주행모드(수직, 롤링, 피칭운동)간의 연성을 고려하여 제어기를 설계할 수 있기 때문에 1/4 car 모델에 비해 제어력의 효 율이 높다는 장점이 있는 반면에 모델이 수학적으로 복잡하므로 제어력을 구하는데 계산량이 많고, 실제 자동차에 적용하기에 복잡하다는 단점을 갖고 있다. 따라서 본 논문에서는 쉽게 실험할 수 있고, 실용화할 수 있는 1/4 car 모델에 대하여 능동제어기를 설계하여 실제자동차에 능동제어기를 적용할 때 참고가 될 수 있도록 하였다. 자동차는 저주파영역의 밴드통과필터 역할 을 하므로 저주파에서의 성능, 특히 탑승자가 민감하게 느끼는 0.5Hz - 10Hz 부근의 주파수성능은 승차감, 조종성에 상당히 중요하다. 이에 본 논문 에서는 0.5Hz - 10Hz 부근의 승차감, 조종성의 향상에 초점을 두고 차체의 속도를 출력변수로 한 LQG/LTR 제어기를 설계하였다. LQG/LTR 설계기법 은 안정도-강인성이 좋은 체계적인 설계기법으로서 전 상태를 측정할 필요 가 없으므로 실제 적용시 효과적이다. 또한 자동차의 제원의 변화에 대한 고 유치의 민감도해석과 새로운 개념으로 안정도-강인성(Robustness)해석을 하 여 수동시스템과 능동시스템의 강인성을 비교하였다.

• Journal of Advanced Navigation Technology
• /
• v.25 no.1
• /
• pp.68-77
• /
• 2021

In this paper, a GPS/MEMS IMU integrated navigation receiver module capable of operating in a high dynamic environment is designed and fabricated, and the results is confirmed. The designed module is composed of RF receiver unit, inertial measurement unit, signal processing unit, correlator, and navigation S/W. The RF receiver performs the functions of low noise amplification, frequency conversion, filtering, and automatic gain control. The inertial measurement unit collects measurement data from a MEMS class IMU applied with a 3-axis gyroscope, accelerometer, and geomagnetic sensor. In addition, it provides an interface to transmit to the navigation S/W. The signal processing unit and the correlator is implemented with FPGA logic to perform filtering and corrrelation value calculation. Navigation S/W is implemented using the internal CPU of the FPGA. The size of the manufactured module is 95.0×85.0×.12.5mm, the weight is 110g, and the navigation accuracy performance within the specification is confirmed in an environment of 1200m/s and acceleration of 10g.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.9
• /
• pp.63-73
• /
• 2015

This work proposes a 2-channel time-interleaved (T-I) 10b 120MS/s pipeline SAR ADC minimizing offset mismatch between channels without any calibration scheme. The proposed ADC employs a 2-channel SAR and T-I topology based on a 2-step pipeline ADC with 4b and 7b in the first and second stage for high conversion rate and low power consumption. Analog circuits such as comparator and residue amplifier are shared between channels to minimize power consumption, chip area, and offset mismatch which limits the ADC linearity in the conventional T-I architecture, without any calibration scheme. The TSPC D flip-flop with a short propagation delay and a small number of transistors is used in the SAR logic instead of the conventional static D flip-flop to achieve high-speed SAR operation as well as low power consumption and chip area. Three separate reference voltage drivers for 4b SAR, 7b SAR circuits and a single residue amplifier prevent undesirable disturbance among the reference voltages due to each different switching operation and minimize gain mismatch between channels. High-frequency clocks with a controllable duty cycle are generated on chip to eliminate the need of external complicated high-frequency clocks for SAR operation. The prototype ADC in a 45nm CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 0.77LSB, with a maximum SNDR and SFDR of 50.9dB and 59.7dB at 120MS/s, respectively. The proposed ADC occupies an active die area of 0.36mm2 and consumes 8.8mW at a 1.1V supply voltage.