• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.12
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• pp.1094-1101
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• 2013

This paper proposes an improved branch predictor that reduces the number execution cycles of applications by selectively accessing a specific element in 4-way associative cache. When a branch instruction is fetched, the proposed branch predictor acquires a branch target address from the selected element in the cache by referring to MRU buffer. Branch prediction rate and application execution speed are considerably improved by increasing the number of BTAC entries in restricted power condition, when compared with that of previous branch predictor which accesses all elements. The effectiveness of the proposed dynamic branch predictor is verified by executing benchmark applications on the core simulator. Experimental results show that number of execution cycles decreases by an average of 10.1%, while power consumption increases an average of 7.4%, when compared to that of a core without a dynamic branch predictor. Execution cycles are reduced by 4.1% in comparison with a core which employs previous dynamic branch predictor.

• The KIPS Transactions:PartA
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• v.14A no.1 s.105
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• pp.55-62
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• 2007

Uptime of embedded processors for mobile devices are dependent on battery consumption. Especially the large portion of power consumption is known to be due to cache management in embedded processors. This paper proposes an energy efficient data cache structure for high performance embedded processors. High performance prefetching data cache issues prefetching instructions before issuing demand-fetch instructions based on reference predictions. These prefetching instruction bring reduction on memory delay by improving cache hit ratio, but on the other hand those increase energy consumption in proportion to the number of prefetching instructions. In this paper, we adopt tag history table on prefetching data cache for reducing energy consumption by minimizing parallel tag comparison. Experimental results show the proposed data cache improves performance on energy consumption as well as memory delay.

• Journal of the Korea Society of Computer and Information
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• v.5 no.3
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• pp.91-98
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• 2000

In this paper we design implement the speaker verification system for verifying personal identification using voice. Filter bank magnitude was used as a feature parameter and code-book was made using LBG a1gorithm. The code book convert feature parameters into code sequence. The difference between reference pattern and input pattern measures using DTW(Dynamic Time Warping). The similarity measured using DTW and threshold value derived from deviation were used to discriminate impostor from client speaker.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.7
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• pp.349-358
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• 2005

False sharing is a result of co-location of unrelated data in the same unit of memory coherency, and is one source of unnecessary overhead being of no help to keep the memory coherency in multiprocessor systems. Moreover. the damage caused by false sharing becomes large in proportion to the granularity of memory coherency. To reduce false sharing in a page-based DSM system, it is necessary to allocate unrelated data objects that have different access patterns into the separate shared pages. In this paper we propose call-site tracing-based shared memory allocator. shortly CSTallocator. CSTallocator expects that the data objects requested from the different call-sites may have different access patterns in the future. So CSTailocator places each data object requested from the different call-sites into the separate shared pages, and consequently data objects that have the same call-site are likely to get together into the same shared pages. We use execution-driven simulation of real parallel applications to evaluate the effectiveness of our CSTallocator. Our observations show that by using CSTallocator a considerable amount of false sharing misses can be additionally reduced in comparison with the existing techniques.

• Journal of Korean Society of Transportation
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• v.27 no.5
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• pp.209-221
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• 2009

Travel time estimation under given traffic conditions is important for providing drivers with travel time prediction information. But the present expressway travel time estimation process cannot calculate a reliable travel time. The objective of this study is to estimate the path travel time spent in a through lane between origin tollgates and destination tollgates on an expressway as a prerequisite result to offer reliable prediction information. Useful and abundant toll collection system (TCS) data were used. When estimating the path travel time, the path travel time is estimated combining the link travel time obtained through a preprocessing process. In the case of a lack of TCS data, the TCS travel time for previous intervals is referenced using the linear interpolation method after analyzing the increase pattern for the travel time. When the TCS data are absent over a long-term period, the dynamic travel time using the VDS time space diagram is estimated. The travel time estimated by the model proposed can be validated statistically when compared to the travel time obtained from vehicles traveling the path directly. The results show that the proposed model can be utilized for estimating a reliable travel time for a long-distance path in which there are a variaty of travel times from the same departure time, the intervals are large and the change in the representative travel time is irregular for a short period.