• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.157-158
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• 2014

In this paper, a design method for a compact CPW-fed slot antenna using SRRs(split-ring resonators) is studied. The structure of the proposed slot antenna is a rectangular slot antenna loaded with SRR conductors inside the slot to reduce the antenna size. Optimal design parameters are obtained by analyzing the effects of the gap between the SRR conductors and slot, and the width of the SRR conductors on the input reflection coefficient characteristic. The optimized compact slot antenna operating at 2.45 GHz band is fabricated on an FR4 substrate with a dimension of 36 mm by 30 mm. The length of the proposed compact slot antenna is reduced by 14.3% compared to that of a conventional rectangular slot antenna. Experiment results show that the antenna has a desired impedance characteristic with a frequency band of 2.4-2.49 GHz for a VSWR < 2.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.11
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• pp.1377-1383
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• 2019

Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.49-56
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• 2004

The performance of the multiprocessor systems is limited by the several factors. The system performance is affected by the processor speed, memory delay, and interconnection network bandwidth/latency. By the evolution of semiconductor technology, off the shelf microprocessor speed breaks beyond GHz, and the processors can be scalable up to multiprocessor system by connecting through the interconnection networks. In this situation, the system performances are bound by the latencies and the bandwidth of the interconnection networks. SCI, Myrinet, and Gigabit Ethernet are widely adopted as a high-speed interconnection network links for the high performance cluster systems. Performance improvement of the interconnection network can be achieved by the bandwidth extension and the latency minimization. Speed up of the operation clock speed is a simple way to accomplish the bandwidth and latency betterment, while its physical distance makes the difficulties to attain the high frequency clock. Hence the system performance and scalability suffered from the interconnection network limitation. Duplicating the link of the interconnection network is one of the solutions to resolve the bottleneck of the scalable systems. Dual-ring SCI link structure is an example of the interconnection network improvement. In this paper, I propose a network topology and a transaction path algorism, which optimize the latency and the efficiency under the duplicated links. By the simulation results, the proposed structure shows 1.05 to 1.11 times better latency, and exhibits 1.42 to 2.1 times faster execution compared to the dual ring systems.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.110-120
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• 2016

A power-efficient neuromodulator is needed for implantable systems. In spite of their stimulation signal's simplicity of wave shape and waiting time of MCU(micro controller unit) much longer than execution time, there is no consideration for low-power design. In this paper, we propose a novel of low-power algorithm based on the characteristics of stimulation signals. Then, we designed and implement a neuromodulation software that we call NMS(neuro modulation simulation). In order to implement low-power algorithm, first, we analyze running time of every function in existing NMS. Then, we calculate execution time and waiting time for these functions. Subsequently, we estimate the transition time between active mode (AM) and low-power mode (LPM). By using these results, we redesign the architecture of NMS in the proposed low-power algorithm: a stimulation signal divided into a number of segments by using characteristics of the signal from which AM or LPM segments are defined for determining the MCU power reduces to turn off or not. Our experimental results indicate that NMS with low-power algorithm reducing current consumption of MCU by 76.31 percent compared to NMS without low-power algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.71-76
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• 2008

H.264(or MPEG-4/AVC pt.10) is a high performance video coding standard, and is widely used. Variable length code (VLC) of the H.264 standard compresses data using the statistical distribution of values. A decoder parses the compressed bit stream and searches decoded values in lookup tables, and the decoding process is not easy to implement by hardware. We propose an architecture of variable length decoder(VLD) for the H.264 baseline profile(BP) L4. The CAVLD decodes syntax elements using the combination of arithmetic units and lookup tables for the optimized hardware architecture. A barral shifter and a first 1's detector parse NAL bit stream, and are shared by Exp-Golomb decoder and CAVLD. A FIFO memory between CAVLD and the reorder unit and a buffer at the output of the reorder unit eliminate the bottleneck of data stream. The proposed VLD is designed using Verilog-HDL and is implemented using an FPGA. The synthesis result using a 0.18um standard CMOS technology shows that the gate count is 22,604 and the decoder can process HD($1920{\times}1080$) video at 120MHz.

• Journal of Korea Game Society
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• v.12 no.5
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• pp.79-88
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• 2012

In this paper, we present a real-time hand pose recognition method to provide an intuitive user interface through hand poses or movements without a keyboard and a mouse. For this, the areas of right and left hands are segmented from the depth camera image, and noise removal is performed. Then, the rotation angle and the centroid point of each hand area are calculated. Subsequently, a circle is expanded at regular intervals from a centroid point of the hand to detect joint points and end points of the finger by obtaining the midway points of the hand boundary crossing. Lastly, the matching between the hand information calculated previously and the hand model of previous frame is performed, and the hand model is recognized to update the hand model for the next frame. This method enables users to predict the hidden fingers through the hand model information of the previous frame using temporal coherence in consecutive frames. As a result of the experiment on various hand poses with the hidden fingers using both hands, the accuracy showed over 95% and the performance indicated over 32 fps. The proposed method can be used as a contactless input interface in presentation, advertisement, education, and game applications.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.5
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• pp.199-212
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• 2008

Software simulation has been widely used for the design and application development of a large-scale wireless sensor network. The degree of details of the simulation must be high to verify the behavior of the network and to estimate its execution time and power consumption of an application program as accurately as possible. But, as the degree of details becomes higher, the simulation time increases. Moreover, as the number of sensor nodes increases, the time tends to be extremely long. We propose an optimal-synchronous parallel discrete-event simulation method to shorten the time in a large-scale sensor network simulation. In this method, sensor nodes are partitioned into subsets, and each PC that is interconnected with others through a network is in charge of simulating one of the subsets. Results of experiments using the parallel simulator developed in this study show that, in the case of the large number of sensor nodes, the speedup tends to approach the square of the number of PCs participating in the simulation. In such a case, the ratio of the overhead due to parallel simulation to the total simulation time is so small that it can be ignored. Therefore, as long as PCs are available, the number of sensor nodes to be simulated is not limited. In addition, our parallel simulation environment can be constructed easily at the low cost because PCs interconnected through LAN are used without change.

• The KIPS Transactions:PartA
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• v.18A no.3
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• pp.99-108
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• 2011

Processor technology is currently continued to parallel processing techniques, not by only increasing clock frequency of a single processor due to the high technology cost and power consumption. In this paper, a SIMD (Single Instruction Multiple Data) based parallel processor is introduced that efficiently processes massive data inherent in multimedia. In addition, this paper proposes pixel subword parallel processing instructions for the SIMD parallel processor architecture that efficiently operate on the image and video pixels. The proposed pixel subword parallel processing instructions store and process four 8-bit pixels on the partitioned four 12-bit registers in a 48-bit datapath architecture. This solves the overflow problem inherent in existing multimedia extensions and reduces the use of many packing/unpacking instructions. Experimental results using the same SIMD-based parallel processor architecture indicate that the proposed pixel subword parallel processing instructions achieve a speedup of $2.3{\times}$ over the baseline SIMD array performance. This is in contrast to MMX-type instructions (a representative Intel multimedia extension), which achieve a speedup of only $1.4{\times}$ over the same baseline SIMD array performance. In addition, the proposed instructions achieve $2.5{\times}$ better energy efficiency than the baseline program, while MMX-type instructions achieve only $1.8{\times}$ better energy efficiency than the baseline program.

• Korean Journal of Optics and Photonics
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• v.13 no.2
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• pp.146-150
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• 2002

1.55${\mu}{\textrm}{m}$ PnpN optical thyristor as a smart optical switch has potential applications in advanced optical communication systems. PnpP optical thyristors operating at 1.55${\mu}{\textrm}{m}$ are proposed and fabricated for the first time. In the optical thyristors, we employ InGaAs/InP multiple quantum well (MQW) for the active n- and p-layers. The thyristors show sufficiently nonlinear s-shape I-V characteristics and spontaneous emission. In the OFF-state, the device has a high-impedance up to switching voltage of 4.03(V). On the other hand, it has low-impedance and emits spontaneous light as a light-emitting diode in the ON-state voltage of 1.77(V), and switching voltage is changed under several light input conditions. It can be used as a header processor in optical asynchronous transfer mode (ATM), as a hard limiter in optical code division multiple access (CDMA) and as a wavelength converter in optical WDM systems.