• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.24-32
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.27-38
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• 2016

This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of $0.16mm^2$. The proposed composite switching employs the conventional $V_{CM}$-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the $V_{CM}$-based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.

• Cartoon and Animation Studies
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• s.30
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• pp.27-57
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• 2013

Animation which appeared with films in the late 19th century was a medium which came on obtaining nourishment from art historical style of modernism. However, the relation establishment between animation and modernism has been focused mainly on animation shapes, namely painted images. This sprang from explaining the relationship between animation and paintings, and for this reason, discussions of movements in animation were understood in tradition of chromophotograph of Muybridge and Jules Marey, or some characteristics owned by the live-action film. However, movements of animation were essentially different from the indexical sign of films or photogram, and objects of reproduction were different between them. Movements reproduced by animation are not ordinary movements, but expressions of or compressed movements and considerably systematic movements. As a result, these movements are far from reproduction of live-action film photogram. Rather, the logic of movements reproduced by animation comes near to controlling their motion scopes, time, distance etc. after dividing each part of the body. This is concluded in a standpoint of modern mechanism which is represented by Descartes and La Mettrie who tried to understand human body as a exchangeable machine. Design of modern mechanism ranging from modern society to industrial society and the age of modernism came to lead to analysis of physical motions of modern industrial society called composition of efficient movements understanding them as the law of nature rather than movements as nature. In the late 19th century, Taylor, F. W. and Gilbreth, Frank Bunker's studies of workers' working hours and 'motion study' were a way of constituting the frame of machine-human, which indicates that tradition of modern mechanism affected the entire modernism passing through industrial society. Further, we can see that motion studies conducted by them have almost similar characteristics to action analysis to study animation later in the name of 'timing'.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.2 s.332
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• pp.61-74
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• 2005

Digital Multimedia Broadcasting(DMB) is a reliable multi-service system for reception by mobile and portable receivers. DMB system allows interference-free reception under the conditions of multipath propagation and transmission errors using COFDM modulation scheme, simultaneously, needs powerful channel error's correction ability. Viterbi Decoder for DMB receiver uses punctured convolutional code and needs lots of computations for real-time operation. So, it is desired to design a high speed and low-power hardware scheme for Viterbi decoder. This paper proposes a combined add-compare-select(ACS) and path metric normalization(PMN) unit for computation power. The proposed PMN architecture reduces the problem of the critical path by applying fixed value for selection algorithm due to the comparison tree which has a weak point from structure with the high-speed operation. The proposed ACS uses the decomposition and the pre-computation technique for reducing the complicated degree of the adder, the comparator and multiplexer. According to a simulation result, reduction of area $3.78\%$, power consumption $12.22\%$, maximum gate delay $23.80\%$ occurred from punctured viterbi decoder for DMB system.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.40-46
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• 2011

This paper proposes a real-time face detection and tracking system that uses neural oscillators which can be applied to access regulation system or control systems of user authentication as well as a new algorithm. We study a way to track faces using the neural oscillatory network which imitates the artificial neural net of information handing ability of human and animals, and biological movement characteristic of a singular neuron. The system that is suggested in this paper can broadly be broken into two stages of process. The first stage is the process of face extraction, which involves the acquisition of real-time RGB24bit color video delivering with the use of a cheap webcam. LEGION(Locally Excitatory Globally Inhibitory)algorithm is suggested as the face extraction method to be preceded for face tracking. The second stage is a method for face tracking by discovering the leader neuron that has the greatest connection strength amongst neighbor neuron of extracted face area. Along with the suggested method, the necessary element of face track such as stability as well as scale problem can be resolved.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.2
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• pp.177-182
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• 2010

The flow of a universal system-level design methodology consists of system specification, system-level hardware/software partitioning, co-design, co-verification using virtual or physical prototype, and system integration. In the developing process of a hardware component in system, the design phase has been regarded as a phase consuming lots of time and cost. However, the verification phase in which functionality of the designed component is verified has recently been considered as a much important phase. In this paper, the implementation of a verification environment which is based on SystemC infrastructure and verifies the functionality of a hardware component is described. The proposed verification system uses SystemC user-defined channel as communication interface between variables of SystemC module and registers of Verilog module. The functional verification of an UART is performed on the proposed verification system. SystemC provides class library for hardware modeling and has an advantage of being able to design a system consisting hardware and software in higher abstraction level than register transfer level. Source codes of SystemC modules are reusable with a minor adaptation on verifying functionality of another hardware component.

• Journal of Digital Convergence
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• v.12 no.10
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• pp.317-327
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• 2014

To improve the efficiency of wireless channel, IEEE 802.11ac uses the DL MU-MIMO MAC scheme through which an AP transmits multiple frames to different mobile nodes simultaneously. IEEE 802.11ac DL MU-MIMO MAC needs a new step, called as TXOP sharing, between legacy IEEE 802.11n DL SU-MIMO's two operations, the obtaining an EDCA TXOP and the transmitting multiple frames for EDCA TXOP. In the TXOP sharing operation, both wireless channel destinations and frames transmitted for its TXOP period should are determined. So this paper deals with the TXOP sharing for improving IEEE 802.11ac MAC performance. However, the EDCA priority based method mentioned by IEEE 802.11ac standard document not fair among the buffers and the frames of buffers, and occurs in high_loss rate and high_delay about specific buffers. In this paper, we propose a new scheme of the TXOP sharing with sequencing p-AC, s-AC in similar properties, and all S-AC. This method provides a differentiated service without damage of EDCA characteristics.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.178-184
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• 2015

This paper proposes a hardware architecture for high performance Deblocking filter(DBF) in High Efficiency Video Coding for UHD(Ultra High Definition) videos. This proposed hardware architecture which has less processing time has a 4-stage pipelined architecture with two filters and parallel boundary strength module. Also, the proposed filter can be used in low-voltage design by using clock gating architecture in 4-stage pipeline. The segmented memory architecture solves the hazard issue that arises when single port SRAM is accessed. The proposed order of filtering shortens the delay time that arises when storing data into the single port SRAM at the pre-processing stage. The DBF hardware proposed in this paper was designed with Verilog HDL, and was implemented with 22k logic gates as a result of synthesis using TSMC 0.18um CMOS standard cell library. Furthermore, the dynamic frequency can process UHD 8k($7680{\times}4320$) samples@60fps using a frequency of 150MHz with an 8K resolution and maximum dynamic frequency is 285MHz. Result from analysis shows that the proposed DBF hardware architecture operation cycle for one process coding unit has improved by 32% over the previous one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8A
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• pp.1238-1246
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• 2000

In a multi-channel network based on wavelength division multiplexing (WDM), an efficient protocol is needed for transmitter and receiver to be tuned to same wavelength during message transmission time. This paper proposes a message scheduling protocol that can efficiently support variable-sized messages, where tunable transceiver has nonzero tuning time. In this protocol, once a node reserves one data channel, it can persistently use the reserved channel till message transmission is finished. Therefore, overhead due to tuning time of the tunable transceiver can be reduced. Moreover, the protocol does not require any global information. Therefore, it can operate independently of the change of the number of nodes, and any new node can join the network at anytime without requiring network initialization. With this protocol, one can avoid data channel and destination conflicts. The protocol is analyzed with a finite population model and the throughput-delay characteristics are investigated as performance measures.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.24 no.1
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• pp.51-58
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• 2014

A LFSR is commonly used for various stream cryptography applications to generate random numbers. A Leap-ahead LFSR was presented to generate a multi-bits random number per cycle. It only requires a single LFSR and it has an advantages in hardware complexity. However, it suffers from the significant reduction of maximum period of the generated random numbers. This paper presents the new segmented Leap-ahead LFSR to solve this problem. It consists of two segmented LFSRs. We prove the efficiency of the proposed segmented architecture using the precise mathematical analysis. We also demonstrate the proposed comparison results with other counterparts using Xinilx Vertex5 FPGA. The proposed architecture can increase 2.5 times of the maximum period of generated random numbers compared to the typical Leap-ahead architecture.