• Title/Summary/Keyword: 동작분할

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A Research about Open Source Distributed Computing System for Realtime CFD Modeling (SU2 with OpenCL and MPI) (실시간 CFD 모델링을 위한 오픈소스 분산 컴퓨팅 기술 연구)

  • Lee, Jun-Yeob;Oh, Jong-woo;Lee, DongHoon
    • Proceedings of the Korean Society for Agricultural Machinery Conference
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    • 2017.04a
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    • pp.171-171
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    • 2017
  • 전산유체역학(CFD: Computational Fluid Dynamics)를 이용한 스마트팜 환경 내부의 정밀 제어 연구가 진행 중이다. 시계열 데이터의 난해한 동적 해석을 극복하기위해, 비선형 모델링 기법의 일종인 인공신경망을 이용하는 방안을 고려하였다. 선행 연구를 통하여 환경 데이터의 비선형 모델링을 위한 Tensorflow활용 방법이 하드웨어 가속 기능을 바탕으로 월등한 성능을 보임을 확인하였다. 그럼에도 오프라인 일괄(Offline batch)처리 방식의 한계가 있는 인공신경망 모델링 기법과 현장 보급이 불가능한 고성능 하드웨어 연산 장치에 대한 대안 마련이 필요하다고 판단되었다. CFD 해석을 위한 Solver로 SU2(http://su2.stanford.edu)를 이용하였다. 운영 체제 및 컴파일러는 1) Mac OS X Sierra 10.12.2 Apple LLVM version 8.0.0 (clang-800.0.38), 2) Windows 10 x64: Intel C++ Compiler version 16.0, update 2, 3) Linux (Ubuntu 16.04 x64): g++ 5.4.0, 4) Clustered Linux (Ubuntu 16.04 x32): MPICC 3.3.a2를 선정하였다. 4번째 개발환경인 병렬 시스템의 경우 하드웨어 가속는 OpenCL(https://www.khronos.org/opencl/) 엔진을 이용하고 저전력 ARM 프로세서의 일종인 옥타코어 Samsung Exynos5422 칩을 장착한 ODROID-XU4(Hardkernel, AnYang, Korea) SBC(Single Board Computer)를 32식 병렬 구성하였다. 분산 컴퓨팅을 위한 환경은 Gbit 로컬 네트워크 기반 NFS(Network File System)과 MPICH(http://www.mpich.org/)로 구성하였다. 공간 분해능을 계측 주기보다 작게 분할할 경우 발생하는 미지의 바운더리 정보를 정의하기 위하여 3차원 Kriging Spatial Interpolation Method를 실험적으로 적용하였다. 한편 병렬 시스템 구성이 불가능한 1,2,3번 환경의 경우 내부적으로 이미 존재하는 멀티코어를 활용하고자 OpenMP(http://www.openmp.org/) 라이브러리를 활용하였다. 64비트 병렬 8코어로 동작하는 1,2,3번 운영환경의 경우 32비트 병렬 128코어로 동작하는 환경에 비하여 근소하게 2배 내외로 연산 속도가 빨랐다. 실시간 CFD 수행을 위한 분산 컴퓨팅 기술이 프로세서의 속도 및 운영체제의 정보 분배 능력에 따라 결정된다고 판단할 수 있었다. 이를 검증하기 위하여 4번 개발환경에서 운영체제를 64비트로 개선하여 5번째 환경을 구성하여 검증하였다. 상반되는 결과로 64비트 72코어로 동작하는 분산 컴퓨팅 환경에서 단일 프로세서 기반 멀티 코어(1,2,3번) 환경보다 보다 2.5배 내외 연산속도 향상이 있었다. ARM 프로세서용 64비트 운영체제의 완성도가 낮은 시점에서 추후 성공적인 실시간 CFD 모델링을 위한 지속적인 검토가 필요하다.

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Design of Low Power 4th order ΣΔ Modulator with Single Reconfigurable Amplifier (재구성가능 연산증폭기를 사용한 저전력 4차 델타-시그마 변조기 설계)

  • Sung, Jae-Hyeon;Lee, Dong-Hyun;Yoon, Kwang Sub
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.5
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    • pp.24-32
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    • 2017
  • In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

Design and fabrication of GaAs MMIC high power amplfier and microstrip combiner for IMT-2000 handset (IMT-2000 고출력 전력전폭기의 GaAs MMIC화 및 전송결합기 설계 구현에 관한 연구)

  • 정명남;이윤현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.11A
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    • pp.1661-1671
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    • 2000
  • 본 고에서는 한국통신(Korea Telecom) IMT-2000 시험시스템(이하: Trial system 라고 함) 단말기용 전력증폭단으로 적용하기 위한 다단구동증폭기 및 전력증폭기를 GaAs MMIC로 설계 구현하는 기술을 제시하였다. 설계된 구동증폭기는 3단으로구성하여 RF(Radia Frequency) 송신신호(1955$\pm$70MHz)대역에서 2단 (중간단)의 이득 조정범위가 40 dB이상이 될 수 있도록 능동부품인 MESFET를 Cascade 형으로 구성하고 MESFET의 게이트(gate)에 조정전압을 인가하는 증폭기를 설계하여 GaAs MMIC화 1 침(크기4$\times$5 mm)으로 제작하였다. 아울러, 본 논문에서는 제시한 구동증폭기는 동작주파수 대역폭 범위기 3.5배이고 출력전력은 15dBmm 이며, 출력전력이득이 25~27dB이고 반사계수는 -15~20dB이며 이득평탄도 3dB(동작주파수 대역폭내)로써 Trial system용 단말기의 최종단인 전력증폭단의 출력단 특성을 효과적으로 나타내었다. 그리고, 전력 증폭기는 2개의 입력단에서 출력되는 신호를 분배하는 전력분배기와 병렬구조인 4개의 증폭단에서 출력되는 출력신호를 외부에서 접속하는 전력결합기를 접소하여 구성하였으며 RF(Radio Frequency) 주파수(1955 $\pm$70NHz)에서 대역폭을 4배로 설계하여 광대역인 대역폭을 구현하였고 출력전력은 570mW이며, 출력부가효율(PAE; Power Added Efficency)가 -15$\pm$20dB이고, 이득 평탄도(Gain flatness)는 동작주파수 대역내에서 0.5dB이며 입출력 전압정재파비(Input & Output VSWR)가 13이하인 고출력 전력증포기를 GaAs MMIC화 1칩 (크기; 3$\times$4mm)으로 제작하였다.의 다양성이나 편리성으로 변화하는 것이 국적을 바꾸는 것보다 어려운 시 대가 멀지 않은 미래에 도래할 것이다. 신세기 통신 과 SK 텔레콤에는 현재 1,300만명이 넘 는 고객이 있으며. 이들 고객은 어 이상 음성통화 중심의 이동전화 고객이 아니라 신세기 통신과 SK텔레콤이 함께 구축해 나갈 거대란 무선 네트워크 사회에서 정보화 시대를 살아 갈 회원들이다. '컨텐츠의 시대'가 개막되는 것이며, 신세기통신과 SK텔레콤은 선의의 경쟁 과 협력을 통해 이동인터넷 서비스의 컨텐츠를 개발해 나가게 될 것이다. 3배가 높았다. 효소 활성에 필수적인 물의 양에 따른 DIAION WA30의 라세미화 효율에 관하여 실험한 결과, 물의 양이 증가할수록 그 효율은 감소하였다. DIAION WA30을 라세미화 촉매로 사용하여 아이소옥탄 내에서 라세믹 나프록센 2,2,2-트리플로로에틸 씨오에스터의 효소적 DKR 반응을 수행해 보았다. 그 결과 DIAION WA30을 사용하지 않은 경우에 비해 반응 전환율과 생성물의 광학 순도는 급격히 향상되었다. 전통적 광학분할 반응의 최대 50%라는 전환율의 제한이 본 연구에서 찾은 DIAION WA30을 첨가함으로써 성공적으로 극복되었다. 또한 고체 염기촉매인 DIAION WA30의 사용은 라세미화 촉매의 회수 및 재사용이 가능하게 해준다.해준다.다. TN5 세포주를 0.2 L 규모 (1 L spinner flask)oJl에서 세포간의 응집현상 없이 부유배양에 적응,배양시킨 후 세포성장 시기에 따른 발현을 조사한 결과 1 MOI의 감염조건 하에서는 $0.6\times10^6$cell/mL의 early exponential시기의 세포밀도에서 72시간 배양하였을 대 최대 발현양을 나타내었다. 나타내었다. $\beta$4 integrin의 표현이 침투 능력을 높이는 역할을 하나 이때에는 laminin과 같은 리간드와의 특이

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Uplink Relaying Scheme for Efficient Frequency Usage in Cognitive Radio Networks (인지 무선 네트워크 환경에서 효율적인 주파수 활용을 위한 상향링크 릴레이 기법)

  • Kim, Se-Woong;Choi, Jae-Kark;Yoo, Sang-Jo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.4A
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    • pp.356-368
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    • 2011
  • While most of the public radio spectrum bands are allocated to licensed users, cognitive radio has been considered as a promising technology for the efficient spectrum utilization. In this new technology, secondary users opportunistically use the temporally underutilized licensed bands as long as they do not give the harmful interference to primary users. In this paper, we focus on the infra-structured network condition in which the cognitive radio network consists of a cognitive radio base station and multiple secondary users. Upon detecting a primary user, the entire cognitive radio network generally switches to another available channel, even if most of the on-going communications still does not interfere with the primary user. Moreover, the network re-entry process on a new channel causes the service disruption of the on-going communications. For this reason, in this paper, we propose a relaying scheme for efficient frequency usage, in which the secondary user out of the interference range of a primary user performs as a relaying node for the secondary user possibly interfering with a primary user. The entire spectrum switching is not required, and thus, we can avoid the service disruption of the on-going communications as much as possible.

A Lower Bound Estimation on the Number of Micro-Registers in Time-Multiplexed FPGA Synthesis (시분할 FPGA 합성에서 마이크로 레지스터 개수에 대한 하한 추정 기법)

  • 엄성용
    • Journal of KIISE:Computer Systems and Theory
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    • v.30 no.9
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    • pp.512-522
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    • 2003
  • For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Typically, the size of the chip required to implement the circuit depends on both the maximum number of the LUT blocks required to implement the function of each subcircuit and the maximum number of micro-registers to store results over context switches in the same time. Therefore, many partitioning or synthesis methods try to minimize these two factors. In this paper, we present a new estimation technique to find the lower bound on the number of micro-registers which can be obtained by any synthesis methods, respectively, without performing any actual synthesis and/or design space exploration. The lower bound estimation is very important in sense that it greatly helps to evaluate the results of the previous work and even the future work. If the estimated lower bound exactly matches the actual number in the actual design result, we can say that the result is guaranteed to be optimal. In contrast, if they do not match, the following two cases are expected: we might estimate a better (more exact) lower bound or we find a new synthesis result better than those of the previous work. Our experimental results show that there are some differences between the numbers of micro-registers and our estimated lower bounds. One reason for these differences seems that our estimation tries to estimate the result with the minimum micro-registers among all the possible candidates, regardless of usage of other resources such as LUTs, while the previous work takes into account both LUTs and micro-registers. In addition, it implies that our method may have some limitation on exact estimation due to the complexity of the problem itself in sense that it is much more complicated than LUT estimation and thus needs more improvement, and/or there may exist some other synthesis results better than those of the previous work.

Double Precision Integer Divider Using Multiplier (곱셈기를 사용한 배정도 정수 나눗셈기)

  • Song, Hong-Bok;Cho, Gyeong-Yeon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.3
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    • pp.637-647
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    • 2010
  • This paper suggested an algorithm that uses a multiplier, 'w bit $\times$ w bit = 2w bit', to process $\frac{N}{D}$ integer division of 2w bit integer N and w bit integer D. An algorithm suggested of the research, when the divisor D is '$D=0.d{\times}2^L$, 0.5 < 0.d < 1.0', approximate value of $\frac{1}{D}$, '$1.g{\times}2^{-L}$', which satisfies '$0.d{\times}1.g=1+e$, e < $2^{-w}$', is defined as over reciprocal number and the dividend N is segmented in small word more than 'w-3' bit, and partial quotient is calculated by multiplying over reciprocal number in each segmented word, and quotient of double precision integer division is evaluated with sum of partial quotient. The algorithm suggested in this paper doesn't require additional correction, because it can calculate correct reciprocal number. In addition, this algorithm uses only multiplier, so additional hardware for division is not required to implement microprocessor. Also, it shows faster speed than the conventional SRT algorithm. In conclusion, results from this study could be used widely for implementation SOC(System on Chip) and etc. which has been restricted to microprocessor and size of the hardware.

The Segmented Polynomial Curve Fitting for Improving Non-linear Gamma Curve Algorithm (비선형 감마 곡선 알고리즘 개선을 위한 구간 분할 다항식 곡선 접합)

  • Jang, Kyoung-Hoon;Jo, Ho-Sang;Jang, Won-Woo;Kang, Bong-Soon
    • Journal of the Institute of Convergence Signal Processing
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    • v.12 no.3
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    • pp.163-168
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    • 2011
  • In this paper, we proposed non-linear gamma curve algorithm for gamma correction. The previous non-linear gamma curve algorithm is generated by the least square polynomial using the Gauss-Jordan inverse matrix. However, the previous algorithm has some weak points. When calculating coefficients using inverse matrix of higher degree, occurred truncation errors. Also, only if input sample points are existed regular interval on 10-bit scale, the least square polynomial is accurately works. To compensate weak-points, we calculated accurate coefficients of polynomial using eigenvalue and orthogonal value of mat11x from singular value decomposition (SVD) and QR decomposition of vandemond matrix. Also, we used input data part segmentation, then we performed polynomial curve fitting and merged curve fitting results. When compared the previous method and proposed method using the mean square error (MSE) and the standard deviation (STD), the proposed segmented polynomial curve fitting is highly accuracy that MSE under the least significant bit (LSB) error range is approximately $10^{-9}$ and STD is about $10^{-5}$.

Layer 2 Routing with Multi-Spanning Tree Per a Node (노드 당 다중 스패닝 트리를 이용한 2계층 라우팅)

  • Suh, Chang-Jin;Shin, Ji-Soo;Kim, Kyung-Mi
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.9B
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    • pp.751-759
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    • 2008
  • Carrier Ethernet backbone network integrates distributed layer-2 based metro networks. In this networks, Multiple Spanning Tree Protocol (MSTP) has been uscd as a main routing protocol that allows multiple spanning trees in a network. A better routing protocol called IEEE802.1aq - Shortest Path Bridging (SPB) is recently proposed, that generates the shortest spanning tree per a destination node. As SPB provides a routing path per a destination node, there is no way to adapt network traffic at normal condition. If we are free from the principle of "a spanning tree per a destination node", we can achieve adaptive routing. Based on this philosophy, we propose a new spanning tree based protocol - Edge Node Divided Spanning Tree (ENDIST). ENDIST divides an edge node into sub-nodes as many as connecting links from the node and each sub-node generates a single shortest path tree based on SPB. Depending on network or nodal status, ENDIST chooses a better routing path by flow-basis. This added traffic engineering ability contributes to enhanced throughput and reduced delay in backbone networks. The simulation informs us that ENDIST's throughput under heavy load performs about 3.4-5.8 and 1.5-2.0 times compared with STP's and SPB's one respectively. Also, we verified that ENDIST's throughput corresponds to the theoretical upper bound at half of cases we investigated. This means that the proposed ENDIST is a dramatically enhanced and the close-to-perfect spanning tree based routing schemes.

Stacked Pad Area Away Package Modules for a Radio Frequency Transceiver Circuit (RF 송수신 회로의 적층형 PAA 패키지 모듈)

  • Jee, Yong;Nam, Sang-Woo;Hong, Seok-Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.10
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    • pp.687-698
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    • 2001
  • This paper presents a three dimensional stacked pad area away (PAA) package configuration as an implementation method of radio frequency (RF) circuits. 224MHz RF circuits of intelligence traffic system(ITS) were constructed with the stacked PAA RF pakage configuration. In the process of manufacturing the stacked PAA RF pakage, RF circuits were partitioned to subareas following their function and operating frequency. Each area of circuits separated to each subunits. The operating characteristics of RF PAA package module and the electrical properties of each subunits were examined. The measurement of electrical parameters for solder balls which were interconnects for stacked PAA RF packages showed that the parasitic capacitance and inductance were 30fF and 120pH, respectively, which might be negligible in PAA RF packaging system. HP 4396B network/spectrum analyzer revealed that the amplification gain of a receiver and transmitter at 224 MHz was 22dB and 27dB, respectively. The gain was 3dB lower than designed values. The difference was probably generated from fabrication process of the circuits by employing commercial standard

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A Practical Approximate Sub-Sequence Search Method for DNA Sequence Databases (DNA 시퀀스 데이타베이스를 위한 실용적인 유사 서브 시퀀스 검색 기법)

  • Won, Jung-Im;Hong, Sang-Kyoon;Yoon, Jee-Hee;Park, Sang-Hyun;Kim, Sang-Wook
    • Journal of KIISE:Databases
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    • v.34 no.2
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    • pp.119-132
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    • 2007
  • In molecular biology, approximate subsequence search is one of the most important operations. In this paper, we propose an accurate and efficient method for approximate subsequence search in large DNA databases. The proposed method basically adopts a binary trie as its primary structure and stores all the window subsequences extracted from a DNA sequence. For approximate subsequence search, it traverses the binary trie in a breadth-first fashion and retrieves all the matched subsequences from the traversed path within the trie by a dynamic programming technique. However, the proposed method stores only window subsequences of the pre-determined length, and thus suffers from large post-processing time in case of long query sequences. To overcome this problem, we divide a query sequence into shorter pieces, perform searching for those subsequences, and then merge their results. To verify the superiority of the proposed method, we conducted performance evaluation via a series of experiments. The results reveal that the proposed method, which requires smaller storage space, achieves 4 to 17 times improvement in performance over the suffix tree based method. Even when the length of a query sequence is large, our method is more than an order of magnitude faster than the suffix tree based method and the Smith-Waterman algorithm.