• Journal of KIISE:Computer Systems and Theory
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• v.30 no.5_6
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• pp.258-264
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• 2003

VLIW architecture has emerged as one of the most effective architectures in dealing with multimedia applications. In multimedia applications, there is ample potential for parallelizing the execution of multiple operations because such applications typically have data intensive processing which often has limited data and/or control dependencies. As the degree of instruction-level parallelism increases, non-clustered VLIW architectures scale poorly because of the tremendous register port pressure. Therefore, clustered VLIW architecture is definitely preferred over non-clustered VLIW architecture when a higher degree of parallelizing is possible as in the case of multimedia processing However, having multiple clusters in an architecture implies that the amount of hardware is quite large, and therefore, power consumption becomes a very crucial issue. In this paper, we propose an algorithm to minimize the peak power consumption without incurring little or no delay penalty. The effectiveness of our algorithm has been verified by various sets of experiments, and up to 30.7% reduction in the peak power consumption is observed compared with the results that is optimized to minimize resources only.

• Journal of the Korea Society of Computer and Information
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• v.24 no.11
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• pp.21-27
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• 2019

Recently, embedded systems have been introduced in various fields such as smart factories, industrial drones, and medical robots. Since sensor data collection and IoT functions for machine learning and big data processing are essential in embedded systems, it is essential to port the operating system that is suitable for the function requirements. However, in embedded systems, it is necessary to separate the hard real-time system, which must process within a fixed time according to service characteristics, and the flexible real-time system, which is more flexible in processing time. It is difficult to port the operating system to a low-performance embedded device such as 8BIT MCU to perform simultaneous real-time. When porting a real-time OS (RTOS) to a low-specification MCU and performing a number of tasks, the performance of the real-time and general processing greatly deteriorates, causing a problem of re-designing the hardware and software if a hard real-time system is required for an operating system ported to a low-performance MCU such as an 8BIT MCU. Research on the technology that can process real-time processing system requirements on RTOS (ported in low-performance MCU) is needed.

• Journal of the Korea Society of Computer and Information
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• v.29 no.7
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• pp.1-9
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• 2024

In this paper, we propose BRAIDS, a boot storm mitigation plan consisting of an AI-based VDI usage prediction system and a virtual machine boot scheduler system, to alleviate boot storms and improve service stability. Virtual Desktop Infrastructure (VDI) is an important technology for improving an organization's work productivity and increasing IT infrastructure efficiency. Boot storms that occur when multiple virtual desktops boot simultaneously cause poor performance and increased latency. Using the xgboost algorithm, existing VDI usage data is used to predict future VDI usage. In addition, it receives the predicted usage as input, defines a boot storm considering the hardware specifications of the VDI server and virtual machine, and provides a schedule to sequentially boot virtual machines to alleviate boot storms. Through the case study, the VDI usage prediction model showed high prediction accuracy and performance improvement, and it was confirmed that the boot storm phenomenon in the virtual desktop environment can be alleviated and IT infrastructure can be utilized efficiently through the virtual machine boot scheduler.

• The KIPS Transactions:PartA
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• v.16A no.6
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• pp.463-472
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• 2009

Real-time operating systems must have satisfying various conditions such as effective scheduling policies, minimized interrupt delay, resolved priority inversion problems, and its applications to be completed within desired deadline. The real-time operating systems, therefore, should be designed and developed to be optimal for these requirements. MicroC/OS-II, a kind of Real-time operating systems, uses the basic priority inheritance with a mutex to solve priority inversion problems. For the implementation of mutex, the kernel in an operating system should provide supports for numerous tasks with same priority. However, MicroC/OS-II does not provide this support for the numerous tasks of same priority. To solve this problem, MicroC/OS-II cannot but using priority reservation, which leads to the waste of unnecessary resources. In this study, we have dealt with new design a protocol, so called TPSP(Temporary Priority Swap Protocol), by an effective solution for above-mentioned problem, eventually enabling embedded systems with constrained resources environments to run applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.19-28
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• 2005

In this paper, we proposed a parallel fast 2-D discrete wavelet transform hardware architecture based on lifting scheme. The proposed architecture improved the 2-D processing speed, and reduced internal memory buffer size. The previous lifting scheme based parallel 2-D wavelet transform architectures were consisted with row direction and column direction modules, which were pair of prediction and update filter module. In 2-D wavelet transform, column direction processing used the row direction results, which were not generated in column direction order but in row direction order, so most hardware architecture need internal buffer memory. The proposed architecture focused on the reducing of the internal memory buffer size and the total calculation time. Reducing the total calculation time, we proposed a 4-way data flow scheduling and memory based parallel hardware architecture. The 4-way data flow scheduling can increase the row direction parallel performance, and reduced the initial latency of starting of the row direction calculation. In this hardware architecture, the internal buffer memory didn't used to store the results of the row direction calculation, while it contained intermediate values of column direction calculation. This method is very effective in column direction processing, because the input data of column direction were not generated in column direction order The proposed architecture was implemented with VHDL and Altera Stratix device. The implementation results showed overall calculation time reduced from $N^2/2+\alpha$ to $N^2/4+\beta$, and internal buffer memory size reduced by around $50\%$ of previous works.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.8B
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• pp.509-520
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• 2007

In this paper, we propose a real-time sensor node platform that guarantees the real-time scheduling of periodic and aperiodic tasks through a multitask-based software decomposition technique. Since existing sensor networking operation systems available in literature are not capable of supporting the real-time scheduling of periodic and aperiodic tasks, the preemption of aperiodic task with high priority can block periodic tasks, and so periodic tasks are likely to miss their deadlines. This paper presents a comprehensive evaluation of how to structure periodic or aperiodic task decomposition in real-time sensor-networking platforms as regard to guaranteeing the deadlines of all the periodic tasks and aiming to providing aperiodic tasks with average good response time. A case study based on real system experiments is conducted to illustrate the application and efficiency of the multitask-based dynamic component execution environment in the sensor node equipped with a low-power 8-bit microcontroller, an IEEE802.15.4 compliant 2.4GHz RF transceiver, and several sensors. It shows that our periodic and aperiodic task decomposition technique yields efficient performance in terms of three significant, objective goals: deadline miss ratio of periodic tasks, average response time of aperiodic tasks, and processor utilization of periodic and aperiodic tasks.

• Journal of KIISE:Information Networking
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• v.35 no.2
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• pp.130-138
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• 2008

The scheme for recognizing the channel availability is one of the most important research issues in cognitive radio systems utilizing unused frequency bands. In this paper, we propose a novel scheme of selecting sensing channel in order to improve the sensing ability of frequency status in cognitive radio ad hoc networks. To fully exploit the sensing ability of each cognitive radio user, we adopt a master for a cluster which is made of several cognitive radio users. By gathering and analyzing the sensing information from cognitive radio users in the cluster, the cooperative sensing is realized. Since the transmission range of a licensed user is limited, it is possible that a master determines different sensing channels to each cognitive radio users based on their location. By making cognitive radio users sense different channels, the proposed scheme can recognize the state of wireless spectrum fast and precisely. Using the simulation, we compare the performance of the proposed scheme with those of two different compared schemes that one makes cognitive radio users recognize the frequency status based on their own sensing results and the other shares frequency status information but does not utilize the location information of licensed user. Simulation results show that the proposed scheme provides available channels as many as possible while detecting the activation of licensed user immediately.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.1
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• pp.9-26
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• 2005

In the pursuit of ever higher levels of performance, recent computer systems have made use of deep pipeline, dynamic scheduling and multi-issue superscalar processor technologies. In this situations, branch prediction schemes are an essential part of modem microarchitectures because the penalty for a branch misprediction increases as pipelines deepen and the number of instructions issued per cycle increases. In this paper, we propose a novel branch prediction scheme, direction-gshare(d-gshare), to improve the prediction accuracy. At first, we model a neural network with the components that possibly affect the branch prediction accuracy, and analyze the variation of their weights based on the neural network information. Then, we newly add the component that has a high weight value to an original gshare scheme. We simulate our branch prediction scheme using Simple Scalar, a powerful event-driven simulator, and analyze the simulation results. Our results show that, compared to bimodal, two-level adaptive and gshare predictor, direction-gshare predictor(d-gshare. 3) outperforms, without additional hardware costs, by up to 4.1% and 1.5% in average for the default mont of embedded direction, and 11.8% in maximum and 3.7% in average for the optimal one.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.989-992
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• 1999

Battery로 작동되고, 소형인 제품들도 다양한 기능은 물론이고, 다양한 입출력 장치를 갖추고, 실시간으로 처리하는 시스템이 많이 요구되고 있는 실정이며, 점차 더욱 더 요구될 것으로 전망된다. 더욱이 포터블 기기는 일반적으로 MCU의 내부에 제한된 ROM type 메모리를 내장하게 되면, 데이터 메모리로 SRAM 및 flash memory를 갗추고 있다. 따라서 이러한 제한된 하드웨어 환경하에서 많은 기능을 수행해야 하는 경우가 많다. 여러 기능을 시간적인 간격으로 배분하거나, 기능 자체를 서로 배분하면서, 서로 융합하는 등의 여러 가지 기능을 수행하려다보면, 당연히 메인 소프트웨어 구조가 복잡해지며 대부분 어셈블리나 C와 같은 linear한 구조를 가지는 language로 개발되기 때문에 효과적인 프로그램 구조를 세우기는 쉽지 않다. 본 논문에서는 이를 위해 좀더 규격화된 방법을 제시하고자 한다. 보다 구체적인 구조를 연구할 목적으로 다양한 테스크를 수행하여야 하는 시스템이면서 프로세서가 필요한 포터블 기기의 한 응용 제품인 MP3 Player 에서 요구되는 job scheduling을 연구한다. 필요한 작업의 종류는 가장 부하가 많이 걸리는 압축된 MP3 file을 다시 복원시켜주는 codec 부분과 일정 시간 간격을 가지고 수행하여야 하는 외부 키보드 입력과 실시간으로 시간을 계산하는 타이머 기능, 그리고 LCD에 시간의 변화를 표시하여 주어야한다. 이와같이 수시로 작업이 발생하지만 시간 점유율이 중간 정도인 LCD 컨트롤과 메모리 컨트롤 등이다. 프로세서의 속도를 최소한으로 줄이면서 스케줄링에 의해 시간 문제를 해결하는 방법을 제시하도록 한다. 이는 기초과학 수준이 높은 북방권 국가들의 과학자들이 주로 활용되고 있다는 점에서도 잘 알 수 있으며 우리의 과학기술 약점을 보완하는 원천으로써 외국인 연구 인력이 대안이 되고 있음을 시사한다. 본 연구에서는 한국 연구 조직에서 일하는 외국인 연구자들의 동기 및 성과에 영향을 미치는 많은 요인들을 확인할 수 있었다. 상관관계, 분산분석, 회귀분석 등을 통해 활용 성과에 미치는 영향 요인들을 도출하였다. 설문 분석을 통하여 동기 및 성과 사이에는 강한 상관관계가 존재하는 것을 확인할 수 있었으며 이는 전통적인 동기 이론들과 부합한다. 대부분의 변수가 동기 및 성과에 동시에 영향을 미치는 것으로 조사되었으며 그중에서도 조직 협력 문화, 외국인 연구자의 의사소통 및 협력성, 외국인 연구자의 연구 능력 관련 변수들 및 연구 프로젝트의 기술수명주기, 외국인 연구자의 기존 기술지식의 흡수 등이 가장 중요한 변수로 나타났다. 이는 우리가 주로 중국 및 러시아 과학자들을 활용하여 상업화하는 외국인 연구인력 활용 패턴과도 일치하는 결과이다. 즉 우호적인 조직문화를 가지고 있는 연구 조직에서, 이미 과학기술 지식을 많이 가지고 있고 연구 능력도 높은 외국인 과학기술자를, 한국에서 기술이 태동 또는 성장하고 있는 연구 분야에서 활용하는 것이 가장 성과가 좋다는 사실을 확인시켜 주고 있다. 국내에서 최초로 수행된 본 연구는 외국인 연구 인력의 활용 성과가 매우 높으며, 우리의 과학기술혁신시스템을 보완하는 유효한 수단으로써 외국인 연구 인력이 중요한 대안이 될 수 있음을 발견하였다. 외국인 연구 인력을 잘 활용하기 위하여 문제점 및 개선방안을 활용 환경, 연구 인력이 중요한 대안이 될 수

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1922-1931
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• 1999

A multicast traffic’s feature is the function of providing a point to multipoints cell transmission, which is emerging from the main function of ATM switch. However, when a conventional point-to-point switch executes a multicast function, the excess load is occurred because unicast cell as well as multicast cell passed the copy network. Additionally, due to the excess load, multicast cells collide with other cells in a switch. Thus a deadlock that losses cells raises, extremely diminishes the performance of switch. An input queued switch also has a defect of the HOL (Head of Line) blocking that less lessens the performance of the switch. In the proposed multicast switch, we use shared memory switch to reduce HOL blocking and deadlock. In order to decrease switch’s complexity and cell's processing time, to improve a throughput, we utilize the method that routes a cell on a separated paths by traffic pattern and the scheduling algorithm that processes a maximum 2N cell at once in the control part. Besides, when cells is congested at an output port, a cell loss probability increases. Thus we use the Output Memory (OM) to reduce the cell loss probability. And we make use of the method that stores the assigned memory (UM, MM) with a cell by a traffic pattern and clears the cell of the Output memory after a fixed saving time to improve the memory utilization rate. The performance of the proposed switch is executed and compared with the conventional policy under the burst traffic condition through both the analysis based on Markov chain and simulation.